Datasheet

System and Peripheral Control Registers www.ti.com
2.5.3.20 Peripheral Power-Down Set Register 3 (PSPWRDWNSET3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-91 and described in Table 2-105.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-91. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) (offset = 8Ch)
31 0
PS[31-24]QUAD[3-0]PWRDWNSET
R/WP-1
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-105. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) Field Descriptions
Bit Field Value Description
31-0 PS[31-24]QUAD[3-0] Peripheral select quadrant clock power-down set.
PWRDWNSET
0 Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1 Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET3 and PSPWRDWNCLR3 registers is set
to 1.
2.5.3.21 Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0)
There is one bit for each quadrant for PS0 to PS7. The protection scheme is described in
Section 2.5.3.17. This register is shown in Figure 2-92 and described in Table 2-106.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-92. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) (offset = A0h)
31 0
PS[7-0]QUAD[3-0]PWRDWNCLR
R/WP-1
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-106. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) Field Descriptions
Bit Field Value Description
31-0 PS[7-0]QUAD[3-0] Peripheral select quadrant clock power-down clear.
PWRDWNCLR
0 Read: The clock to the peripheral select quadrant is active.
Write: The bit is unchanged.
1 Read: The clock to the peripheral select quadrant is inactive.
Write: The corresponding bit in PSPWRDWNSET0 and PSPWRDWNCLR0 registers is
cleared to 0.
220
Architecture SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated