Datasheet

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2.5.3.12 Peripheral Protection Clear Register 3 (PPROTCLR3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-83 and described in Table 2-97.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-83. Peripheral Protection Clear Register 3 (PPROTCLR3) (offset = 4Ch)
31 0
PCS[31-24]QUAD[3-0]PROTCLR
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-97. Peripheral Protection Clear Register 3 (PPROTCLR3) Field Descriptions
Bit Field Value Description
31-0 PCS[31-24]QUAD[3-0] Peripheral select quadrant protection clear.
PROTCLR
0 Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET3 and PMPROTCLR3 registers is cleared to 0.
2.5.3.13 Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0)
Each bit corresponds to a bit at the same index in the PMPROT register in that they both relate to the
same peripheral. This register is shown in Figure 2-84 and described in Table 2-98.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-84. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) (offset = 60h)
31 0
PCS[31-0]PWRDNSET
R/WP-1
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-98. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) Field Descriptions
Bit Field Value Description
31-0 PCS[31-0]PWRDNSET Peripheral memory clock power-down set.
0 Read: The peripheral memory clock[31-0] is active.
Write: The bit is unchanged.
1 Read: The peripheral memory clock[31-0] is inactive.
Write: The corresponding bit in the PCSPWRDWNSET0 and PCSPWRDWNCLR0 registers
is set to 1.
215
SPNU562–May 2014 Architecture
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