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System and Peripheral Control Registers
2.5.3.8 Peripheral Protection Set Register 3 (PPROTSET3)
There is one bit for each quadrant for PS24 to PS31. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-79 and described in Table 2-93.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-79. Peripheral Protection Set Register 3 (PPROTSET3) (offset = 2Ch)
31 0
PCS[31-24]QUAD[3-0]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-93. Peripheral Protection Set Register 3 (PPROTSET3) Field Descriptions
Bit Field Value Description
31-0 PCS[31-24]QUAD[3-0] Peripheral select quadrant protection set.
PROTSET
0 Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET3 and PMPROTCLR3 registers is set to 1.
2.5.3.9 Peripheral Protection Clear Register 0 (PPROTCLR0)
There is one bit for each quadrant for PS0 to PS7. The protection scheme is described in Section 2.5.3.5.
This register is shown in Figure 2-80 and described in Table 2-94.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-80. Peripheral Protection Clear Register 0 (PPROTCLR0) (offset = 40h)
31 0
PCS[7-0]QUAD[3-0]PROTCLR
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-94. Peripheral Protection Clear Register 0 (PPROTCLR0) Field Descriptions
Bit Field Value Description
31-0 PCS[7-0]QUAD[3-0] Peripheral select quadrant protection clear.
PROTCLR
0 Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is cleared to 0.
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SPNU562May 2014 Architecture
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