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2.5.3.6 Peripheral Protection Set Register 1 (PPROTSET1)
There is one bit for each quadrant for PS8 to PS15. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-77 and described in Table 2-91.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-77. Peripheral Protection Set Register 1 (PPROTSET1) (offset = 24h)
31 0
PCS[15-8]QUAD[3-0]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-91. Peripheral Protection Set Register 1 (PPROTSET1) Field Descriptions
Bit Field Value Description
31-0 PCS[15-8]QUAD[3-0] Peripheral select quadrant protection set.
PROTSET
0 Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is set to 1.
2.5.3.7 Peripheral Protection Set Register 2 (PPROTSET2)
There is one bit for each quadrant for PS16 to PS23. The protection scheme is described in
Section 2.5.3.5. This register is shown in Figure 2-78 and described in Table 2-92.
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-78. Peripheral Protection Set Register 2 (PPROTSET2) (offset = 28h)
31 0
PCS[23-16]QUAD[3-0]PROTSET
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-92. Peripheral Protection Set Register 2 (PPROTSET2) Field Descriptions
Bit Field Value Description
31-0 PCS[23-16]QUAD[3-0] Peripheral select quadrant protection set.
PROTSET
0 Read: The peripheral select quadrant can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET2 and PMPROTCLR2 registers is set to 1.
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Architecture SPNU562–May 2014
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