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System and Peripheral Control Registers

2.5.2.7 Clock Slip Control Register (CLKSLIP)

This register is shown in Figure 2-65 and described in Table 2-78. For information on filtering the FBSLIP,

see Section 2.5.1.34.

Figure 2-65. Clock Slip Control Register (CLKSLIP) (offset = 70h)

31 16

Reserved

R-0

15 14 13 8 7 4 3 0

Reserved PLL1_RFSLIP_FILTER_COUNT Reserved PLL1_RFSLIP_FILTER_KEY

R-0 R/WP-0 R-0 R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-78. Clock Slip Control Register (CLKSLIP) Field Descriptions

Bit Field Value Description

31-14 Reserved 0 Read returns 0. Writes have no effect.

13-8 PLL1_RFSLIP_FILTER_COUNT Configure the count for the filtered PLL1 RFSLIP. Count is on 10M clock. On

reset, counter value is zero. Counter must be programmed to non-zero value and

enabled for the filtering to be enabled

0 Filtering is disabled. Every slip is recognized.

1h Filtering is enabled. Every slip is recognized.

2h Filtering is enabled. The slip must be at least 2 HF LPO cycles wide in order to

be recognized as a slip.

: :

3Fh Filtering is enabled. The RFSLIP must be at least 63 HF LPO cycles wide in

order to be recognized as a slip.

7-4 Reserved 0 Read returns 0. Writes have no effect.

3-0 PLL1_RFSLIP_FILTER_KEY Enable the PLL1 RFSLIP filtering.

5h On reset, the PLL1 RFSLIP filter is disabled and normal PLL1 RFSLIP passes

through.

Fh This is an unsupported value. Avoid writing this value to this field.

Others Enable PLL1 RFSLIP filtering. Recommended to program Ah in these bit fields.

Enable of PLL1 RFSLIP occurs when the KEY is programmed and a non-zero

value is present in the COUNT field.

199

SPNU562–May 2014 Architecture

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