Datasheet

System and Peripheral Control Registers

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2.5.2.6 HCLK Control Register (HCLKCNTL)

This register is shown in Figure 2-64 and described in Table 2-77.

Figure 2-64. HCLK Control Register (HCLKCNTL) (offset = 54h)

31 16

Reserved

R-0

15 2 1 0

Reserved HCLKR

R-0 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-77. HCLK Control Register (HCLKCNTL) Field Descriptions

Bit Field Value Description

31-2 Reserved 0 Read returns 0. Writes have no effect.

1-0 HCLKR HCLK divider value. The value of HCLKR bits determine the HCLK frequency as a ratio of GCLK.

0 HCLK is equal to GCLK divide by 1

1h HCLK is equal to GCLK divide by 2

2h HCLK is equal to GCLK divide by 3

3h HCLK is equal to GCLK divide by 4

198

Architecture SPNU562–May 2014

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