Datasheet

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System and Peripheral Control Registers

Table 2-76. Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1)

Field Descriptions (continued)

Bit Field Value Description

10-8 VCLKA3R Clock divider for the VCLKA3 source. Output will be present on VCLKA3_DIVR.

VCLKA3 domain will be enabled by writing to the CDDIS register and VCLKA3_DIV_CDDIS bit

It can inferred that VCLKA3_DIV clock is disabled when VCLKA3_S clock is disabled.

0 The ratio is VCLKA3 divided by 1.

: :

7h The ratio is VCLKA3 divided by 8.

7-5 Reserved 0 Read returns 0. Writes have no effect.

4 VCLKA3_DIV_CDDIS Disable the VCLKA3 divider output.

VCLKA3 domain will be enabled by writing to the CDDIS register

0 Enable the prescaled VCLKA3 clock on VCLKA3_DIVR.

1 Disable the prescaled VCLKA3 clock on VCLKA3_DIVR.

3-0 VCLKA3S Peripheral asynchronous clock3 source.

0 Clock source0 is the source for peripheral asynchronous clock3.

1h Clock source1 is the source for peripheral asynchronous clock3.

2h Clock source2 is the source for peripheral asynchronous clock3.

3h Clock source3 is the source for peripheral asynchronous clock3.

4h Clock source4 is the source for peripheral asynchronous clock3.

5h Clock source5 is the source for peripheral asynchronous clock3.

6h Clock source6 is the source for peripheral asynchronous clock3.

7h Clock source7 is the source for peripheral asynchronous clock3.

8h-Fh VCLK is the source for peripheral asynchronous clock3.

NOTE: Nonimplemented clock sources should not be enabled or used. A list of the available clock

sources is shown in the Table 2-29.

197

SPNU562–May 2014 Architecture

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