Datasheet
System and Peripheral Control Registers
www.ti.com
2.5.2.5 Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1)
This register is shown in Figure 2-63 and described in Table 2-76.
Figure 2-63. Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1) [offset = 40h]
31 27 26 24
Reserved VCLKA4R
R-0 R/WP-1h
23 21 20 19 16
Reserved VCLKA4_DIV_ VCLKA4S
CDDIS
R-0 R/WP-0 R/WP-9h
15 11 10 8
Reserved VCLKA3R
R-0 R/WP-1h
7 5 4 3 0
Reserved VCLKA3_DIV_ VCLKA3S
CDDIS
R-0 R/WP-0 R/WP-9h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-76. Peripheral Asynchronous Clock Configuration 1 Register (VCLKACON1)
Field Descriptions
Bit Field Value Description
31-27 Reserved 0 Read returns 0. Writes have no effect.
26-24 VCLKA4R Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR.
VCLKA4 domain will be enabled by writing to the CDDIS register and VCLKA4_DIV_CDDIS bit
It can inferred that VCLKA4_DIV clock is disabled when VCLKA4_S clock is disabled.
0 The ratio is VCLKA4 divided by 1.
: :
7h The ratio is VCLKA4 divided by 8.
23-21 Reserved 0 Read returns 0. Writes have no effect.
20 VCLKA4_DIV_CDDIS Disable the VCLKA4 divider output.
VCLKA4 domain will be enabled by writing to the CDDIS register
0 Enable the prescaled VCLKA4 clock on VCLKA4_DIVR.
1 Disable the prescaled VCLKA4 clock on VCLKA4_DIVR.
19-16 VCLKA4S Peripheral asynchronous clock4 source.
0 Clock source0 is the source for peripheral asynchronous clock4.
1h Clock source1 is the source for peripheral asynchronous clock4.
2h Clock source2 is the source for peripheral asynchronous clock4.
3h Clock source3 is the source for peripheral asynchronous clock4.
4h Clock source4 is the source for peripheral asynchronous clock4.
5h Clock source5 is the source for peripheral asynchronous clock4.
6h Clock source6 is the source for peripheral asynchronous clock4.
7h Clock source7 is the source for peripheral asynchronous clock4.
8h-Fh VCLK is the source for peripheral asynchronous clock4.
15-11 Reserved 0 Read returns 0. Writes have no effect.
196
Architecture SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated