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System and Peripheral Control Registers

2.5.2.4 Clock 2 Control Register (CLK2CNTRL)

This register is shown in Figure 2-62 and described in Table 2-75.

Figure 2-62. Clock 2 Control Register (CLK2CNTRL) (offset = 3Ch)

31 16

Reserved

R-0

15 12 11 8 7 4 3 0

Reserved Reserved Reserved VCLK3R

R-0 R/WP-1h R-0 R/WP-1h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-75. Clock 2 Control Register (CLK2CNTRL) Field Descriptions

Bit Field Value Description

31-12 Reserved 0 Read returns 0. Writes have no effect.

11-8 Reserved Reads return value and writes allowed in privilege mode.

7-4 Reserved 0 Read returns 0. Writes have no effect.

3-0 VCLK3R VBUS clock3 ratio.

0 The ratio is HCLK divide by 1.

: :

Fh The ratio is HCLK divided by 16.

195

SPNU562–May 2014 Architecture

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