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System and Peripheral Control Registers

2.5.1.42 Clock Control Register (CLKCNTL)

The CLKCNTL register, shown in Figure 2-49 and described in Table 2-61, controls peripheral reset and

the peripheral clock divide ratios.

NOTE: VCLK and VCLK2 clock ratio restrictions.

VCLK2 must always be greater than or equal to VCLK. In addition, the VCLK and VCLK2

clock ratios must not be changed simultaneously. The application must configure the VCLK2

ratio, read back the contents of the CLKCNTL register, and then configure the VCLK ratio.

Figure 2-49. Clock Control Register (CLKCNTL) (offset = D0h)

31 28 27 24 23 20 19 16

Reserved VCLK2R Reserved VCLKR

R-0 R/WP-1h R-0 R/WP-1h

15 9 8 7 0

Reserved PENA Reserved

R-0 R/WP-0 R-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-61. Clock Control Register (CLKCNTL) Field Descriptions

Bit Field Value Description

31-28 Reserved 0 Read returns 0. Writes have no effect.

27-24 VCLK2R VBUS clock2 ratio.

0 The VCLK2 speed is HCLK divided by 1.

: :

Fh The VCLK2 speed is HCLK divided by 16.

23-20 Reserved 0 Read returns 0. Writes have no effect.

19-16 VCLKR VBUS clock ratio.

0 The VCLK speed is HCLK divided by 1.

: :

Fh The VCLK speed is HCLK divided by 16.

15-9 Reserved 0 Read returns 0. Writes have no effect.

8 PENA Peripheral enable bit. The application must set this bit before accessing any peripheral

0 The global peripheral/peripheral memory frames are in reset.

1 All peripheral/peripheral memory frames are out of reset.

7-0 Reserved 0 Read returns 0. Writes have no effect.

181

SPNU562–May 2014 Architecture

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