Datasheet

RM57L843

SPNS215C –FEBRUARY 2014–REVISED JUNE 2016

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harsh environments (for example, automotive and industrial fields) that require reliable serial

communication or multiplexed wiring. The Ethernet module supports MII, RMII, and Management Data I/O

(MDIO) interfaces. The I2C module is a multimaster communication module providing an interface

between the microcontroller and an I

C-compatible device through the I

C serial bus. The I2C module

supports speeds of 100 and 400 kbps.

The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module multiplies the external frequency

reference to a higher frequency for internal use. The Global Clock Module (GCM) manages the mapping

between the available clock sources and the internal device clock domains.

The device also has two External Clock Prescaler (ECP) modules. When enabled, the ECPs output a

continuous external clock on the ECLK1 and ECLK2 balls. The ECLK frequency is a user-programmable

ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored

externally as an indicator of the device operating frequency.

The Direct Memory Access (DMA) controller has 32 channels, 48 peripheral requests, and ECC protection

on its memory. An MPU is built into the DMA to protect memory against erroneous transfers.

The Error Signaling Module (ESM) monitors on-chip device errors and determines whether an interrupt or

external Error pin/ball (nERROR) is triggered when a fault is detected. The nERROR signal can be

monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides a memory extension to asynchronous and synchronous

memories or other slave devices.

A Parameter Overlay Module (POM) is included to enhance the debugging capabilities of application code.

The POM can reroute flash accesses to internal RAM or to the EMIF, thus avoiding the reprogramming

steps necessary for parameter updates in flash. This capability is particularly helpful during real-time

system calibration cycles.

Several interfaces are implemented to enhance the debugging capabilities of application code. In addition

to the built-in ARM Cortex-R5F CoreSight debug features, the Embedded Cross Trigger (ECT) supports

the interaction and synchronization of multiple triggering events within the SoC. An External Trace

Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes,

a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral

accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write

external data into the device memory. Both the RTP and DMM have no or minimal impact on the program

execution time of the application code.

With integrated safety features and a wide choice of communication and control peripherals, the

RM57L843 device is an ideal solution for high-performance real-time control applications with safety-

critical requirements.

(1) For more information on these devices, see Section 10, Mechanical Packaging and Orderable

Information.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE

RM57L843ZWT NFBGA (337) 16.00 mm × 16.00 mm