Datasheet

System and Peripheral Control Registers www.ti.com
2.5.1.34 General Purpose Register (GPREG1)
This register is shown in Figure 2-41 and described in Table 2-53. For information on filtering the RFSLIP,
see Section 2.5.2.7.
Figure 2-41. General Purpose Register (GPREG1) (offset = A0h)
31 26 25 20 19 16
Reserved PLL1_FBSLIP_FILTER_COUNT PLL1_FBSLIP_FILTER_KEY
R-0 R/WP-0 R/WP-0
15 0
Reserved
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-53. General Purpose Register (GPREG1) Field Descriptions
Bit Field Value Description
31-26 Reserved 0 Read returns 0. Writes have no effect.
25-20 PLL1_FBSLIP_FILTER_ FBSLIP down counter programmed value.
COUNT
Configures the system response when a FBSLIP is indicated by the PLL macro.
When PLL1_FBSLIP_FILTER_KEY is not Ah, the down counter counts from the
programmed value on every LPO high-frequency clock once PLL macro indicates
FBSLIP. When the count reaches 0, if the synchronized FBSLIP signal is still high, an
FBSLIP condition is indicated to the system module and is captured in the global
status register. When the FBSLIP signal from the PLL macro is de-asserted before
the count reaches 0, the counter is reloaded with the programmed value.
0 Filtering is disabled. Every slip is recognized.
1h Filtering is enabled. Every slip is recognized.
2h Filtering is enabled. The slip must be at least 2 HF LPO cycles wide in order to be
recognized as a slip.
: :
3Fh Filtering is enabled. The slip must be at least 63 HF LPO cycles wide in order to be
recognized as a slip.
19-16 PLL1_FBSLIP_FILTER_ Configures the system response when a FBSLIP is indicated by the PLL macro.
KEY
5h FBSLIP filtering is bypassed and the FBSLIP indicated by the PLL macro is captured
in the system module global status register.
Ah FBSLIP filtering is enabled and the one-stage synchronization circuit is used.
Fh FBSLIP filtering is enabled and the two-stage synchronization circuit is used.
All other FBSLIP filtering is enabled.
values
15-0 Reserved 0 Read returns 0s or 1s and write in privilege mode. The functionality of this bit is
unavailable in this device.
174
Architecture SPNU562–May 2014
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