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System and Peripheral Control Registers

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2.5.1.32 DFT Control Register (DFTCTRLREG)

This register is shown in Figure 2-39 and described in Table 2-51.

Figure 2-39. DFT Control Register (DFTCTRLREG) (offset = 90h)

31 16

Reserved

R-0

15 14 13 12 11 10 9 8 7 4 3 0

Reserved DFTWRITE Reserved DFTREAD Reserved TEST_MODE_KEY

R-0 R/WP-1h R-0 R/WP-1h R-0 R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-51. DFT Control Register (DFTCTRLREG) Field Descriptions

Bit Field Value Description

31-14 Reserved 0 Read returns 0. Writes have no effect.

13-12 DFTWRITE DFT logic access.

For F021:

DFTWRITE[0] = 0 and DFTREAD[0] = 0 configured in stress mode

DFTWRITE[1] = 0 and DFTREAD[1] = 0 configured in stress mode

DFTWRITE[0] = 0 and DFTREAD[0] = 0 configured in fast mode

DFTWRITE[1] = 1 and DFTREAD[1] = 1 configured in fast mode

DFTWRITE[0] = 1 and DFTREAD[0] = 1 configured in slow mode

DFTWRITE[1] = 0 and DFTREAD[1] = 0 configured in slow mode

DFTWRITE[0] = 1 and DFTREAD[0] = 1 configured in screen mode

DFTWRITE[1] = 1 and DFTREAD[1] = 1 configured in screen mode

11-10 Reserved 0 Read returns 0. Writes have no effect.

9-8 DFTREAD DFT logic access.

For F021:

DFTWRITE[0] = 0 and DFTREAD[0] = 0 configured in stress mode

DFTWRITE[1] = 0 and DFTREAD[1] = 0 configured in stress mode

DFTWRITE[0] = 0 and DFTREAD[0] = 0 configured in fast mode

DFTWRITE[1] = 1 and DFTREAD[1] = 1 configured in fast mode

DFTWRITE[0] = 1 and DFTREAD[0] = 1 configured in slow mode

DFTWRITE[1] = 0 and DFTREAD[1] = 0 configured in slow mode

DFTWRITE[0] = 1 and DFTREAD[0] = 1 configured in screen mode

DFTWRITE[1] = 1 and DFTREAD[1] = 1 configured in screen mode

7-4 Reserved 0 Read returns 0. Writes have no effect.

3-0 TEST_MODE_KEY Test mode key. This register is for internal TI use only.

0 - Fh Register key disable. All bits in this register will maintain their default value and cannot be

(except Ah) written.

Ah Register key enable. ALL the bits can be written to only when the key is enabled. On reset,

these bits will be set to 0x5.

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Architecture SPNU562–May 2014

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