Datasheet

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Table 2-50. Clock Test Register (CLKTEST) Field Descriptions (continued)
Bit Field Value Description
11-8 SEL_GIO_PIN GIOB[0] pin clock source valid, clock source select
0 Oscillator valid status
1h PLL clock status
2h Reserved
3h Reserved
4h Reserved
5h High frequency clock LPO (Low Power Oscillator) clock valid status
6h Secondary PLL free-running clock output valid status
7h Reserved
8h Low frequency clock LPO (Low Power Oscillator) clock
9h Oscillator valid status
Ah Oscillator valid status
Bh Oscillator valid status
Ch Oscillator valid status
Dh Oscillator valid status
Eh Oscillator valid status
Fh Oscillator valid status
7-4 Reserved 0 Read returns 0. Writes have no effect.
3-0 SEL_ECP_PIN ECLK pin clock source select
Note: Only valid clock sources can be selected for the ECLK pin. Valid clock
sources are displayed by the CSVSTAT register.
0 Oscillator clock
1h PLL clock
2h Not Implemented
3h EXTCLKIN1
4h Low frequency LPO (Low Power Oscillator) clock
5h High frequency clock LPO (Low Power Oscillator) clock
6h Secondary PLL free-running clock output
7h EXCLKIN2
8h GCLK
9h RTI Base
Ah Not Implemented
Bh VCLKA1
Ch VCLKA2
Dh VCLKA3_S
Eh VCLKA4
Fh Flash HD Pump Oscillator
NOTE: Nonimplemented clock sources should not be enabled or used.
171
SPNU562–May 2014 Architecture
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