Datasheet

www.ti.com

System and Peripheral Control Registers

2.5.1.23 MSTC Global Status Register (MSTCGSTAT)

The MSTCGSTAT register, shown in Figure 2-30 and described in Table 2-42, shows the status of the

memory hardware initialization and the memory self-test.

Figure 2-30. MSTC Global Status Register (MSTCGSTAT) (offset = 68h)

31 16

Reserved

R-0

15 9 8 7 1 0

Reserved MINIDONE Reserved MSTDONE

R-0 R/WPC-0 R-0 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; C = Clear; WP = Write in privileged mode only; -n = value after reset

Table 2-42. MSTC Global Status Register (MSTCGSTAT) Field Descriptions

Bit Field Value Description

31-9 Reserved 0 Read returns 0. Writes have no effect.

8 MINIDONE Memory hardware initialization complete status.

Note: Disabling the MINITGENA key (By writing from a Ah to any other value) will clear the

MINIDONE status bit to 0.

Note: Individual memory initialization status is shown in the MINISTAT register.

0 Read: Memory hardware initialization is not complete for all memory.

Write: A write of 0 has no effect.

1 Read: Hardware initialization of all memory is completed.

Write: The bit is cleared to 0.

7-1 Reserved 0 Read returns 0. Writes have no effect.

0 MSTDONE Memory self-test run complete status.

Note: Disabling the MSTGENA key (by writing from a Ah to any other value) will clear the

MSTDONE status bit to 0.

0 Read: Memory self-test is not completed.

Write: A write of 0 has no effect.

1 Read: Memory self-test is completed.

Write: The bit is cleared to 0.

161

SPNU562–May 2014 Architecture

Submit Documentation Feedback