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System and Peripheral Control Registers

2.5.1.21 Memory Hardware Initialization Global Control Register (MINITGCR)

The MINITGCR register, shown in Figure 2-28 and described in Table 2-40, enables automatic hardware

memory initialization.

Figure 2-28. Memory Hardware Initialization Global Control Register (MINITGCR) (offset = 5Ch)

31 16

Reserved

R-0

15 4 3 0

Reserved MINITGENA

R-0 R/WP-5h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-40. Memory Hardware Initialization Global Control Register (MINITGCR) Field Descriptions

Bit Field Value Description

31-4 Reserved 0 Read returns 0. Writes have no effect.

3-0 MINITGENA Memory hardware initialization global enable key.

Ah Global memory hardware initialization is enabled.

Others Global memory hardware initialization is disabled.

Note: It is recommended that a value of 5h be used to disable memory hardware

initialization. This value will give maximum protection from an event that would

inadvertently enable the controller.

159

SPNU562–May 2014 Architecture

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