Datasheet

System and Peripheral Control Registers

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2.5.1.20 Memory Self-Test Global Control Register (MSTGCR)

The MSTGCR register, shown in Figure 2-27 and described in Table 2-39, controls several aspects of the

PBIST (Programmable Built-In Self Test) memory controller.

Figure 2-27. Memory Self-Test Global Control Register (MSTGCR) (offset = 58h)

31 24 23 16

Reserved Reserved

R-0 R/WP-0

15 10 9 8 7 4 3 0

Reserved ROM_DIV Reserved MSTGENA

R-0 R/WP-0 R-0 R/WP-5h

LEGEND: R = Read only; R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset

Table 2-39. Memory Self-Test Global Control Register (MSTGCR) Field Descriptions

Bit Field Value Description

31-24 Reserved 0 Read returns 0. Writes have no effect.

23-16 Reserved Read returns 0 or 1 depends on what is written in privileged mode. The functionality of

these bits are unavailable in this device.

15-10 Reserved 0 Read returns 0. Writes have no effect.

9-8 ROM_DIV Prescaler divider bits for ROM clock source.

0 ROM clock source is GCLK divided by 1.PBIST will reset for 16 VBUS cycles.

1h ROM clock source is GCLK divided by 2.PBIST will reset for 32 VBUS cycles.

2h ROM clock source is GCLKJ divided by 4.PBIST will reset for 64 VBUS cycles.

3h ROM clock source is GCLK divided by 8.PBIST will reset for 96 VBUS cycles.

7-4 Reserved 0 Read returns 0. Writes have no effect.

3-0 MSTGENA Memory self-test controller global enable key

Note: Enabling the MSTGENA key will generate a reset to the state machine of the

selected PBIST controller.

Ah Memory self-test controller is enabled.

Others Memory self-test controller is disabled.

Note: It is recommended that a value of 0101b be used to disable the memory self-

test controller. This value will give maximum protection from a bit flip inducing event

that would inadvertently enable the controller.

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Architecture SPNU562–May 2014

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