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System and Peripheral Control Registers www.ti.com
2.5.1.18 RTI Clock Source Register (RCLKSRC)
The RCLKSRC register, shown in Figure 2-25 and described in Table 2-37, controls the RTI (Real Time
Interrupt) clock source selection.
NOTE: Important constraint when the RTI clock source is not VCLK
If the RTIx clock source is chosen to be anything other than the default VCLK, then the RTI
clock needs to be at least three times slower than the VCLK. This can be achieved by
configuring the RTIxCLK divider in this register. This divider is internally bypassed when the
RTIx clock source is VCLK.
Figure 2-25. RTI Clock Source Register (RCLKSRC) (offset = 50h)
31 16
Reserved
R-0
15 10 9 8 7 4 3 0
Reserved RTIDIV Reserved RTISRC
R-0 R/WP-1h R-0 R/WP-9h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-37. RTI Clock Source Register (RCLKSRC) Field Descriptions
Bit Field Value Description
31-10 Reserved 0 Read returns 0. Writes have no effect.
9-8 RTIDIV RTI clock Divider.
0 RTICLK divider value is 1.
1h RTICLK divider value is 2.
2h RTICLK divider value is 4.
3h RTICLK divider value is 8.
7-4 Reserved 0 Read returns 0. Writes have no effect.
3-0 RTISRC RTI clock source.
0 Clock source0 is the source for RTICLK.
1h Clock source1 is the source for RTICLK.
2h Clock source2 is the source for RTICLK.
3h Clock source3 is the source for RTICLK.
4h Clock source4 is the source for RTICLK.
5h Clock source5 is the source for RTICLK.
6h Clock source6 is the source for RTICLK.
7h Clock source7 is the source for RTICLK.
8h-Fh VCLK is the source for RTICLK.
NOTE: A list of the available clock sources is shown in the Table 2-29.
156
Architecture SPNU562–May 2014
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