Datasheet

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2.5.1.13 Clock Domain Disable Register (CDDIS)
The CDDIS register, shown in Figure 2-20 and described in Table 2-32, controls the state of the clock
domains.
NOTE: All the clock domains are enabled on wakeup.
The application should guarantee that when HCLK and VCLK_sys are turned off through the
HCLKOFF bit, the GCLK domain is also turned off.
Figure 2-20. Clock Domain Disable Register (CDDIS) (offset = 3Ch)
31 16
Reserved
R-0
15 12 11 10 9 8
Reserved VCLKA4OFF Reserved Reserved VCLK3OFF
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
7 6 5 4 3 2 1 0
Reserved RTICLKOFF VCLKA2OFF VCLKA1OFF VCLK2OFF VCLKPOFF HCLKOFF GCLKOFF
R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-32. Clock Domain Disable Register (CDDIS) Field Descriptions
Bit Field Value Description
31-12 Reserved 0-1 Read returns 0 or 1 and privilege mode writes allowed.
11 VCLKA4OFF VCLKA4 domain off.
0 The VCLKA4 domain is enabled.
1 The VCLKA4 domain is disabled.
10-9 Reserved 0-1 Reads return 0 or 1 and privilege mode writes allowed.
8 VCLK3OFF VCLK3 domain off.
0 The VCLK3 domain is enabled.
1 The VCLK3 domain is disabled.
7 Reserved 0 Reads return 0 or 1 and privilege mode writes allowed.
6 RTICLKOFF RTICLK domain off.
0 The RTICLK domain is enabled.
1 The RTICLK domain is disabled.
5-4 VCLKA[2-1]OFF VCLKA[2-1] domain off.
0 The VCLKA[2-1] domain is enabled.
1 The VCLKA[2-1] domain is disabled.
3 VCLK2OFF VCLK2 domain off.
0 The VCLK2 domain is enabled.
1 The VCLK2 domain is disabled.
2 VCLKPOFF VCLK_periph domain off.
0 The VCLK_periph domain is enabled.
1 The VCLK_periph domain is disabled.
1 HCLKOFF HCLK and VCLK_sys domains off.
0 The HCLK and VCLK_sys domains are enabled.
1 The HCLK and VCLK_sys domains are disabled.
0 GCLKOFF GCLK domain off.
0 The GCLK domain is enabled.
1 The GCLK domain is disabled.
149
SPNU562–May 2014 Architecture
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