Datasheet

System and Peripheral Control Registers

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2.5.1.12 Clock Source Disable Clear Register (CSDISCLR)

The CSDISCLR register, shown in Figure 2-19 and described in Table 2-31, clears clock sources to the

enabled state.

Figure 2-19. Clock Source Disable Clear Register (CSDISCLR) (offset = 38h)

31 8

Reserved

R-0

7 6 5 4 3 2 1 0

CLRCLKSR7 CLRCLKSR6 CLRCLKSR5 CLRCLKSR4 CLRCLKSR3 Reserved CLRCLKSR1 CLRCLKSR0

OFF OFF OFF OFF OFF OFF OFF

R/WP-1 R/WP-1 R/WP-0 R/WP-0 R/WP-1 R-1 R/WP-1 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-31. Clock Source Disable Clear Register (CSDISCLR) Field Descriptions

Bit Field Value Description

31-8 Reserved 0 Reads return 0. Writes have no effect.

7-3 CLRCLKSR[7-3]OFF Enables clock source[7-3].

0 Read: Clock source[7-3] is disabled.

Write: Clock source[7-3] is unchanged.

1 Read: Clock source[7-3] is enabled.

Write: Clock source[7-3] is set to the enabled state.

Note: After a new clock source disable bit is set via the CSDISSET register, the new

status of the bit will be reflected in the CSDIS register (offset 30h), the CSDISSET

2 Reserved Reads return 1. Writes have no effect.

1-0 CLRCLKSR[1-0]OFF Enables clock source[1-0].

0 Read: Clock source[1-0] is disabled.

Write: Clock source[1-0] is unchanged.

1 Read: Clock source[1-0] is enabled.

Write: Clock source[1-0] is set to the enabled state.

Note: After a new clock source disable bit is set via the CSDISSET register, the new

status of the bit will be reflected in the CSDIS register (offset 30h), the CSDISSET

NOTE: A list of the available clock sources is shown in the Table 2-29.

148

Architecture SPNU562–May 2014

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