Datasheet

www.ti.com

System and Peripheral Control Registers

2.5.1.11 Clock Source Disable Set Register (CSDISSET)

The CSDISSET register, shown in Figure 2-18 and described in Table 2-30, sets clock sources to the

disabled state.

Figure 2-18. Clock Source Disable Set Register (CSDISSET) (offset = 34h)

31 8

Reserved

R-0

7 6 5 4 3 2 1 0

SETCLKSR7 SETCLKSR6 SETCLKSR5 SETCLKSR4 SETCLKSR3 Reserved SETCLKSR1 SETCLKSR0

OFF OFF OFF OFF OFF OFF OFF

R/WP-1 R/WP-1 R/WP-0 R/WP-0 R/WP-1 R-1 R/WP-1 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset

Table 2-30. Clock Source Disable Set Register (CSDISSET) Field Descriptions

Bit Field Value Description

31-8 Reserved 0 Reads return 0. Writes have no effect.

7-3 SETCLKSR[7-3]OFF Set clock source[7-3] to the disabled state.

0 Read: Clock source[7-3] is enabled.

Write: Clock source[7-3] is unchanged.

1 Read: Clock source[7-3] is disabled.

Write: Clock source[7-3] is set to the disabled state.

Note: After a new clock source disable bit is set via the CSDISSET register, the new

status of the bit will be reflected in the CSDIS register (offset 30h), the CSDISSET

2 Reserved Reads return 1. Writes have no effect.

1-0 SETCLKSR[1-0]OFF Set clock source[1-0] to the disabled state.

0 Read: Clock source[1-0] is enabled.

Write: Clock source[1-0] is unchanged.

1 Read: Clock source[1-0] is disabled.

Write: Clock source[1-0] is set to the disabled state.

Note: After a new clock source disable bit is set via the CSDISSET register, the new

status of the bit will be reflected in the CSDIS register (offset 30h), the CSDISSET

NOTE: A list of the available clock sources is shown in the Table 2-29.

147

SPNU562–May 2014 Architecture

Submit Documentation Feedback