Datasheet

Clocks

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2.4.5 Embedded Trace Macrocell (ETM-R5)

The RM57Lx microcontrollers contain an ETM-R5 module with a 32-bit internal data port. The ETM-R5

module is connected to a TPIU with a 32-bit data bus; the TPIU provides a 35-bit (32-bit data and 3-bit

control) external interface for trace. The ETM-R5 is CoreSight compliant and follows the ETM v3

specification; for more details see the ARM CoreSight ETM-R5 TRM specification.

The ETM clock source is selected as either VCLK or the external ETMTRACECLKIN pin. The selection is

done by the EXTCTLOUT control bits of the TPIU EXTCTL_Out_Port register. The address of this register

is TPIU base address + 0x404.

Before you begin accessing TPIU registers, the TPIU should be unlocked via the CoreSight key and 1h or

2h should be written to this register.

Figure 2-6. EXTCTL_Out_Port Register [offset = 404h]

31 16

Reserved

R-0

15 2 1 0

Reserved EXTCTLOUT

R-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-13. EXTCTL_Out_Port Register Field Descriptions

Bit Field Value Description

31-2 Reserved 0 Read returns 0. Writes have no effect.

1-0 EXTCTLOUT EXTCTL output control.

0 Tied-zero

1h VCLK

2h ETMTRACECLKIN

3h Tied-zero

2.4.6 Safety Considerations for Clocks

The RM57Lx microcontrollers are targeted for use in several safety-critical applications. The following

sections describe the internal or external monitoring mechanisms that detect and signal clock source

failures.

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Architecture SPNU562–May 2014

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