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2.4.3 Low Power Modes
All clock domains are active in the normal operating mode. This is the default mode of operation. As
described in Section 2.4.1.1 and Section 2.4.2.1, the application can choose to disable any particular clock
source and domain that it does not plan to use. Also, the peripheral central resource controller (PCR) has
control registers to enable / disable the peripheral clock (VCLK) for each peripheral select. This offers the
application a large number of choices for enabling / disabling clock sources, or clock domains, or clocks to
specific peripherals.
This section describes three particular low-power modes and their typical characteristics. They are not the
only low-power modes configurable by the application, as just described.
Table 2-11. Typical Low-Power Modes
Suggested
Active
Mode Active Clock Wake Up Wake Up Time(wake up detected -to- CPU
Clock Wake Up Options
Name Source(s) Clock code execution start)
Domain(s)
Source(s)
Flash pump sleep -> active transition time
RTI interrupt,
+
GIO interrupt,
Doze Main oscillator RTICLK Main oscillator Flash bank sleep -> standby transition time
CAN message,
+
SCI message
Flash bank standby -> active transition time
HF LPO warm start-up time
+
RTI interrupt,
Flash pump sleep -> active transition time
GIO interrupt,
Snooze LF LPO RTICLK HF LPO +
CAN message,
Flash bank sleep -> standby transition time
SCI message
+
Flash bank standby -> active transition time
HF LPO warm start-up time
+
GIO interrupt, Flash pump sleep -> active transition time
Sleep None None CAN message, HF LPO +
SCI message Flash bank sleep -> standby transition time
+
Flash bank standby -> active transition time
133
SPNU562–May 2014 Architecture
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