Datasheet

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Table 2-10. Clock Domains (continued)
Clock Disable Default Source Selection
Clock Domain Bit Source Register Special Considerations
• Defaults to VCLK as the source
• If a clock source other than VCLK is selected for
RTICLK, then the RTICLK frequency must be less
RTICLK CDDIS.6 VCLK RCLKSRC[3:0]
than or equal to VCLK/3
• Application can ensure this by programming the
RTIDIV field of the RCLKSRC register, if necessary
• Is disabled via the CDDISx registers bit 6
2.4.2.1 Enabling / Disabling Clock Domains
Each clock domain can be independently enabled or disabled using the set of Clock Domain Disable
registers – CDDIS, CDDISSET and CDDISCLR.
Each bit in these registers corresponds to the clock domain number indicated in Table 2-10. For example,
setting bit 1 in the CDDIS or CDDISSET registers disables the HCLK clock domain. The clock domain will
be turned off only when every module that uses the HCLK domain gives the “permission” for HCLK to be
turned off.
All clock domains are enabled by default, or upon a system reset, or whenever a wake up condition is
detected.
2.4.2.2 Mapping Clock Sources to Clock Domains
Each clock domain needs to be mapped to a valid clock source. There are control registers that allow an
application to choose the clock sources for each clock domain.
• Selecting clock source for GCLKx, HCLK and VCLKx domains
The CPU clock (GCLK1 and GCLK2), the system module clock (HCLK), and the peripheral bus clocks
(VCLKx) all use the same clock source. This clock source is selected via the GHVSRC register. The
default source for the GCLKx, HCLK and VCLKx is the main oscillator. That is, after power up, the GCLKx
and HCLK are running at the OSCIN frequency, while the VCLKx frequency is the OSCIN frequency
divided by 2.
• Selecting clock source for VCLKA1 and VCLKA2 domains
The clock source for VCLKA1 and VCLKA2 domains is selected via the VCLKASRC register. The default
source for the VCLKA1 and VCLKA2 domains is the VCLK.
• Selecting clock source for VCLKA4 domain
The clock source for VCLKA4 domain is selected via the VCLKACON1 register. The default source for the
VCLKA4 domain is the VCLK.
• Selecting clock source for RTICLK domain
The clock source for RTICLK domain is selected via the RCLKSRC register. The default source for the
RTICLK domain is the VCLK.
NOTE: Selecting a clock source for RTICLK that is not VCLK
When the application chooses a clock source for RTICLK domain that is not VCLK, then the
application must ensure that the resulting RTICLK frequency must be less than or equal to
VCLK frequency divided by 3. The application can configure the RTIDIV field of the
RCLKSRC register for dividing the selected clock source frequency by 1, 2, 4 or 8 to meet
this requirement.
132
Architecture SPNU562–May 2014
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