Datasheet

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2.4.2 Clock Domains
The clocking on this device is divided into multiple clock domains for flexibility in control as well as clock
source selection. There are 10 clock domains on this device. Each of these are described in Table 2-10.
Each of the control registers listed in Table 2-10 are defined in Section 2.5. The AC timing characteristics
for each clock domain are specified in the device data manual.
Table 2-10. Clock Domains
Clock Disable Default Source Selection
Clock Domain Bit Source Register Special Considerations
• This the main clock from which HCLK is divided
down
• In phase with HCLK
• Is disabled separately from HCLK via the CDDISx
GCLK1 CDDIS.0 OSCIN GHVSRC[3:0]
registers bit 0
• Can be divided by 1 up to 8 when running CPU self-
test (LBIST) using the CLKDIV field of the
STCCLKDIV register at address 0xFFFFE108
• Divided from GCLK1 via HCLKCNTL register
HCLK CDDIS.1 OSCIN GHVSRC[3:0]
• Allowable clock ratio from 1:1 to 4:1
• Is disabled via the CDDISx registers bit 1
• Divided down from HCLK via CLKCNTL register
• Can be HCLK/1, HCLK/2,... or HCLK/16
• Is disabled separately from HCLK via the CDDISx
VCLK CDDIS.2 OSCIN GHVSRC[3:0]
registers bit 2
• HCLK:VCLK2:VCLK must be integer ratios of each
other
• Divided down from HCLK
• Can be HCLK/1, HCLK/2,... or HCLK/16
• Frequency must be an integer multiple of VCLK
VCLK2 CDDIS.3 OSCIN GHVSRC[3:0]
frequency
• Is disabled separately from HCLK via the CDDISx
registers bit 3
• Divided down from HCLK
• Can be HCLK/1, HCLK/2,... or HCLK/1
VCLK3 CDDIS.8 OSCIN GHVSRC[3:0]
• HCLK:VCLK3 must be integer ratios of each other
• Is disabled separately from HCLK via the CDDISx
registers bit 8
• Defaults to VCLK as the source
VCLKA1 CDDIS.4 VCLK VCLKASRC[3:0]
• Frequency can be as fast as HCLK frequency
• Is disabled via the CDDISx registers bit 4
• Defaults to VCLK as the source
VCLKA2 CDDIS.5 VCLK VCLKASRC[3:0]
• Frequency can be as fast as HCLK frequency
• Is disabled via the CDDISx registers bit 5
• Defaults to VCLK as the source
VCLKA4_S CDDIS.11 VCLK VCLKACON1[19:16]
• Frequency can be as fast as HCLK frequency
• Is disabled via the CDDISx registers bit 11
• Divided down from VCLKA4_S using the VCLKA4R
field of the VCLKACON1 register
• Frequency can be VCLKA4_S/1, VCLKA4_S/2, ..., or
VCLKA4_S/8
VCLKA4_DIVR VCLKACON1.20 VCLK VCLKACON1[19:16]
• Default frequency is VCLKA4_S/2
• Is disabled separately via the VCLKACON1
register's VCLKA4_DIV_CDDIS bit if the VCLKA4_S
is not already disabled
131
SPNU562–May 2014 Architecture
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