Datasheet

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2.4 Clocks
This section describes the clocking structure of the RM57Lx microcontrollers.
2.4.1 Clock Sources
The devices support up to 7 clock sources. These are shown in Table 2-9. The electrical specifications as
well as timing requirements for each of the clock sources are specified in the device data manual.
Table 2-9. Clock Sources
Clock Source # Clock Source Name Description
Main oscillator. This is the primary clock for the microcontroller and is the
0 OSCIN only clock that is input to the phase-locked loops. The oscillator frequency
must be between 5 and 20 MHz.
This is the output of the main PLL. The PLL is capable of modulating its
1 PLL #1
output frequency in a controlled manner to reduce the radiated emissions.
This clock source is not available and must not be enabled or used as
2 Not implemented
source for any clock domain.
External clock input 1. A square wave input can be applied to this device
3 EXTCLKIN1
input and used as a clock source inside the device.
This is the low-frequency output of the internal reference oscillator. This is
LF LPO (Low-Frequency
4 typically an 80 KHz signal which is used by the real-time interrupt module
LPO)
for generating periodic interrupts to wake up from a low power mode.
This is the high-frequency output of the internal reference oscillator. This is
HF LPO (High-Frequency
5 typically a 10 MHz signal which is used by the clock monitor module as a
LPO)
reference clock to monitor the main oscillator frequency.
This is the output of the second PLL. There is no option of modulating this
PLL’s output signal. This separate non-modulating PLL allows the
6 PLL #2
generation of an asynchronous clock source that is independent of the
CPU clock frequency.
External clock input 2. A square wave input can be applied to this device
7 EXTCLKIN2
input and used as a clock source inside the device.
2.4.1.1 Enabling / Disabling Clock Sources
Each clock source can be independently enabled or disabled using the set of Clock Source Disable
registers – CSDIS, CSDISSET and CSDISCLR.
Each bit in these registers corresponds to the clock source number indicated in Table 2-9. For example,
setting bit 1 in the CSDIS or CSDISSET registers disables the PLL#1.
NOTE: Disabling the Main Oscillator or HF LPO
By default, the clock monitoring circuit is enabled and checks for the main oscillator
frequency to be within a certain range using the HF LPO as a reference. If the main oscillator
and/or the HF LPO are disabled with the clock monitoring still enabled, the clock monitor will
indicate an oscillator fault. The clock monitoring must be disabled before disabling the main
oscillator or the HF LPO clock source(s).
The clock source is only disabled once there is no active clock domain that is using that clock source. Also
check the “Oscillator and PLL” user guide for more information on enabling / disabling the oscillator and
PLL.
On the RM57Lx microcontrollers, the clock sources 0, 4, and 5 are enabled by default.
2.4.1.2 Checking for Valid Clock Sources
The application can check whether a clock source is valid or not by checking the corresponding bit to be
set in the Clock Source Valid Status (CSVSTAT) register. For example, the application can check if bit 1 in
CSVSTAT is set before using the output of PLL#1 as the source for any clock domain.
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Architecture SPNU562–May 2014
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