Datasheet

www.ti.com Memory Organization
Table 2-4. EPC Registers Bit Mapping
Address
Register Name Bit # Error Source Remark
Offset
• Bit associates with the Uncorrectable ECC
error detected by the CPU Interconnect
Uncorrectable ECC for
Subsystem for the DMA interface
0
DMA interface
• See Interconnect chapter for details on the
ECC generation and evaluation for DMA
interface
8h UERRSTAT
• Bit associates with the Uncorrectable ECC
error detected by the CPU Interconnect
Uncorrectable ECC for
Subsystem for the PS_SCR_M interface
1
PS_SCR_M interface
• See Interconnect chapter for details on the
ECC generation and evaluation for DMA
interface
• Bit associates with the FIFO full status for
the interface that is used to capture the CPU
0 CPU Correctable ECC error
correctable error event
• Correctable error event exported by CPU's
event bus.
1 Reserved
• Bit associates with the FIFO full status for
the interface that is used to capture the
Correctable ECC for
DMA correctable error event
2
DMA interface
• Correctable error event detected by the
CPU Interconnect Subsystem for the DMA
PortA interface.
10h FIFOFULLSTAT
• Bit associates with the FIFO full status for
the interface that is used to capture the
Correctable ECC for
PS_SCR_M correctable error event
3
PS_SCR_M interface
• Correctable error event detected by the
CPU Interconnect Subsystem for the
PS_SCR_M interface.
• Bit associates with the FIFO full status for
the interface that is used to capture the L2
SRAM correctable error event
Correctable ECC error from
4
• Correctable error event detected by the L2
L2 SRAM
SRAM wrapper during the read phase of a
Read-Modify-Write operation due to a less
than 64-bit write from the bus master.
• Bit associates with the FIFO overflow status
0 CPU Correctable ECC error
for the interface that is used to capture the
CPU correctable error event
1 Reserved
• Bit associates with the FIFO overflow status
Correctable ECC for
2
for the interface that is used to capture the
DMA interface
14h OVRFLWSTAT DMA correctable error event
• Bit associates with the FIFO overflow status
Correctable ECC for
3
for the interface that is used to capture the
PS_SCR_M interface
PS_SCR_M correctable error event
• Bit associates with the FIFO overflow status
Correctable ECC error from
4
for the interface that is used to capture the
L2 SRAM
L2 SRAM correctable error event
Uncorrectable ECC for
• Uncorrectable error address register for the
20h UERRADDR0 31:0
DMA interface
DMA interface
Uncorrectable ECC for
• Uncorrectable error address register for the
24h UERRADDR1 31:0
PS_SCR_M interface
PS_SCR_M interface
121
SPNU562–May 2014 Architecture
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated