Datasheet

CAM
FIFO
FIFO
FIFO
FIFO
CPU0CorrectableError
CPUSCRCorrectableECCforDMA I/F
CPUSCRCorrectableECCforPS_SCR_MI/F
L2RAMWRMWCorrectableError
Lookup
FSM
ErrGen
ErrStat
ESM
CorrectableErrorCaptureBlock
CPUSCRUncorrectableECCforDMA I/F
CPUSCRUncorrectableECCforPS_SCR_MI/F
ErrGen
UncorrectableErrorCaptureBlock
UERR AddrReg
UERR AddrReg
ErrStat
ErrStat
EPCModule
CorrectableErrorEventSource
UnorrectableErrorEventSource
ch0
ch2
ch3
ch4
ch0
ch1
Memory Organization www.ti.com
Figure 2-4. EPC Integration Diagram
120
Architecture SPNU562–May 2014
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