Datasheet
Memory Organization
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Table 2-2. Module Registers / Memories Memory Map (continued)
Address Range Response for
Access to
Unimplemented
Memory Locations in
Target Name Select Start End Frame Size Actual Size Frame
LIN1 PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B Reads return
zeros, writes
have no effect
SCI3 PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B Reads return
zeros, writes
have no effect
LIN2 PS[6] 0xFFF7_E600 0xFFF7_E6FF 256B 256B Reads return
zeros, writes
have no effect
SCI4 PS[6] 0xFFF7_E700 0xFFF7_E7FF 256B 256B Reads return
zeros, writes
have no effect
MibSPI1 PS[2] 0xFFF7_F400 0xFFF7_F5FF 512B 512B Reads return
zeros, writes
have no effect
MibSPI2 PS[2] 0xFFF7_F600 0xFFF7_F7FF 512B 512B Reads return
zeros, writes
have no effect
MibSPI3 PS[1] 0xFFF7_F800 0xFFF7_F9FF 512B 512B Reads return
zeros, writes
have no effect
MibSPI4 PS[1] 0xFFF7_FA00 0xFFF7_FBFF 512B 512B Reads return
zeros, writes
have no effect
MibSPI5 PS[0] 0xFFF7_FC00 0xFFF7_FDFF 512B 512B Reads return
zeros, writes
have no effect
System Modules Control Registers and Memories under PCR1 (Peripheral Segment 1)
DMA RAM PPCS[0] 0xFFF8_0000 0xFFF8_0FFF 4kB 4kB Abort
VIM RAM PPCS[2] 0xFFF8_2000 0xFFF8_2FFF 4kB 4kB Wrap around for
accesses to
unimplemented
address offsets
lower than
0x2FFF.
RTP RAM PPCS[3] 0xFFF8_3000 0xFFF8_3FFF 4kB 4kB Abort
Flash Wrapper PPCS[7] 0xFFF8_7000 0xFFF8_7FFF 4kB 4kB Abort
eFuse Farm PPCS[12] 0xFFF8_C000 0xFFF8_CFFF 4kB 4kB Abort
Controller
Power Domain PPSE[0] 0xFFFF_0000 0xFFFF_01FF 512B 512B Abort
Control (PMM)
FMTM PPSE[1] 0xFFFF_0400 0xFFFF_05FF 512B 512B Reads return
Note: This module is zeros, writes
only used by TI during have no effect
test
STC2 (NHET1/2) PPSE[2] 0xFFFF_0800 0xFFFF_08FF 256B 256B Reads return
zeros, writes
have no effect
SCM PPSE[2] 0xFFFF_0A00 0xFFFF_0AFF 256B 256B Abort
EPC PPSE[3] 0xFFFF_0C00 0xFFFF_0FFF 1kB 1kB Abort
PCR1 registers PPSE[4]- 0xFFFF_1000 0xFFFF_17FF 2kB 2kB Reads return
PPSE[5] zeros, writes
have no effect
NMPU (PS_SCR_S) PPSE[6] 0xFFFF_1800 0xFFFF_19FF 512B 512B Abort
NMPU (DMA Port A) PPSE[6] 0xFFFF_1A00 0xFFFF_1BFF 512B 512B Abort
116
Architecture SPNU562–May 2014
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