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Table 2-2. Module Registers / Memories Memory Map (continued)
Address Range Response for
Access to
Unimplemented
Memory Locations in
Target Name Select Start End Frame Size Actual Size Frame
MIBADC1 RAM PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128kB 8kB Wrap around for
accesses to
unimplemented
address offsets
lower than
0x1FFF.
MIBADC1 Look-UP 384 bytes Look-Up Table
Table for ADC1
wrapper. Starts
at address offset
0x2000 and
ends at address
offset 0x217F.
Wrap around for
accesses
between offsets
0x0180 and
0x3FFF. Abort
generation for
accesses
beyond offset
0x4000.
NHET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128kB 16kB Wrap around for
accesses to
unimplemented
address offsets
lower than
0x3FFF. Abort
generated for
accesses
beyond 0x3FFF.
NHET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128kB 16kB Wrap around for
accesses to
unimplemented
address offsets
lower than
0x3FFF. Abort
generated for
accesses
beyond 0x3FFF.
HET TU2 RAM PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128kB 1kB Abort
HET TU1 RAM PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128kB 1kB Abort
Coresight Debug Components
CoreSight Debug CSCS[0] 0xFFA0_0000 0xFFA0_0FFF 4kB 4kB Reads return
ROM zeros, writes
have no effect
Cortex-R5F Debug CSCS[1] 0xFFA0_1000 0xFFA0_1FFF 4kB 4kB Reads return
zeros, writes
have no effect
ETM-R5 CSCS[2] 0xFFA0_2000 0xFFA0_2FFF 4kB 4kB Reads return
zeros, writes
have no effect
CoreSight TPIU CSCS[3] 0xFFA0_3000 0xFFA0_3FFF 4kB 4kB Reads return
zeros, writes
have no effect
POM CSCS[4] 0xFFA0_4000 0xFFA0_4FFF 4kB 4kB Reads return
zeros, writes
have no effect
114
Architecture SPNU562–May 2014
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