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Memory Organization
2.2.2 Memory Map Table
The control and status registers for each module are mapped within the CPU’s 4GB memory space. Some
modules also have associated memories, which are also mapped within this space.
Table 2-2 shows the starting and ending addresses of each module’s register frame and any associated
memory. The table also shows the response generated by the module or the interconnect whenever an
access is made to an unimplemented location inside the register or memory frame.
Table 2-2. Module Registers / Memories Memory Map
Address Range Response for
Access to
Unimplemented
Memory Locations in
Target Name Select Start End Frame Size Actual Size Frame
Level 2 Memories
Level 2 Flash Data 0x0000_0000 0x003F_FFFF 4MB 4MB Abort
Space
Level 2 SRAM 0x0800_0000 0x083F_FFFF 4MB 512kB Abort
Level 2 SRAM ECC 0x0840_0000 0x087F_FFFF 4MB 512kB
Accelerator Coherency Port
Accelerator 0x0800_0000 0x087F_FFFF 8MB 512kB Abort
Coherency Port
Level 1 Cache Memories
Cortex-R5F Data 0x3000_0000 0x30FF_FFFF 16MB 32kB Abort
Cache Memory
Cortex-R5F 0x3100_0000 0x31FF_FFFF 16MB 32kB
Instruction Cache
Memory
External Memory Accesses
EMIF Chip Select 2 0x6000_0000 0x63FF_FFFF 64MB 16MB Access to
(asynchronous) Reserved space
EMIF Chip Select 3 0x6400_0000 0x67FF_FFFF 64MB 16MB Generates Abort
(asynchronous)
EMIF Chip Select 4 0x6800_0000 0x6BFF_FFFF 64MB 16MB
(asynchronous)
EMIF Chip Select 0 0x8000_0000 0x87FF_FFFF 128MB 128MB
(synchronous)
Flash OTP, ECC, EEPROM Bank
Customer OTP, 0xF000_0000 0xF000_1FFF 8kB 4kB Abort
Bank0
Customer OTP, 0xF000_2000 0xF000_3FFF 8kB 4kB Abort
Bank1
Customer OTP, 0xF000_E000 0xF000_FFFF 8kB 1kB Abort
EEPROM Bank
Customer OTP-ECC, 0xF004_0000 0xF004_03FF 1kB 512B Abort
Bank0
Customer OTP-ECC, 0xF004_0400 0xF004_07FF 1kB 512B Abort
Bank1
Customer OTP-ECC, 0xF004_1C00 0xF004_1FFF 1kB 128B Abort
EEPROM Bank
TI OTP, Bank0 0xF008_0000 0xF008_1FFF 8kB 4kB Abort
TI OTP, Bank1 0xF008_2000 0xF008_3FFF 8kB 4kB Abort
TI OTP, EEPROM 0xF008_E000 0xF008_FFFF 8kB 1kB Abort
Bank
TI OTP-ECC, Bank0 0xF00C_0000 0xF00C_03FF 1kB 512B Abort
TI OTP-ECC, Bank1 0xF00C_0400 0xF00C_07FF 1kB 512B Abort
111
SPNU562–May 2014 Architecture
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