Datasheet

ID Decode Addr Decode

MasterID Address/Control

MasterID Protection Register N

Peripheral Select N

PCRx

Introduction

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2.1.5 Interconnect Subsystem Runtime Status

Other than the runtime checker status as described in Section 2.1.4, the CPU Interconnect Subsystems

and the Peripheral Interconnect Subsystem in the microcontroller also generates several status onto the

system that are captured in the SCM (SCR Control Module). Table 4-4 lists the SCM register bit mapping.

2.1.6 Master ID to PCRx

The master ID associated with each master port on the Peripheral Interconnect Subsystem contains a 4-

bit value. The master ID is passed along with the address and control signals to three PCR modules. PCR

decodes the address and control signals to select the peripheral. In addition, it decodes this 4-bit master

ID value to perform memory protection. With 4-bit of master ID, it allows the PCR to distinguish among 16

different masters to allow or dis-allow access to a given peripheral. Associated with each peripheral a 16-

bit Master ID access protection register is defined. Each bit grants or denies the permission of the

corresponding binary coded decimal masterID. For example, if bit 5 of the access permission register is

set, it grants master ID 5 to access the peripheral. If bit 7 is clear, it denies master ID 7 to access the

peripheral. Figure 2-2 illustrates the Master-ID filtering scheme. The master ID of each master which is

capable of accessing the PCRx is listed in Table 4-1. Also see Section 2.5.3 for details on the registers

definition.

Figure 2-2. PCR MasterID Filtering

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Architecture SPNU562–May 2014

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