Datasheet

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Table 2-1. Definition of Terms (continued)
Acronym/Term Full Form Description
CPU CPU Side Switched Central This is one of the two main SCRs in the device. It arbitrates between the
Interconnect Resource Controller accesses from multiple bus masters to the bus slaves using a round robin
Subsystem priority scheme. This interconnect subsystem contains diagnostic logic to
perform parity checking on address and control signals from bus masters, parity
checking on response signals from slaves, ECC generation and evaluation on
the datapath for transactions initiated by the non-CPU masters and also self
test logic to diagnose itself.
Peripheral Peripheral Side Switched This is one of the two main SCRs in the device. It arbitrates between the
Interconnect Central Resource Controller accesses from multiple bus masters to the bus slaves using a round robin
Subsystem priority scheme.
CRCx Cyclic Redundancy Checker The CRC module provides two channels to perform background signature
verification on any memory region using a 64-bit maximum-length linear
feedback shift register (LFSR) . The CRC module is a bus slave in this device.
Flash Memory Level 2 Flash Memory There are two slave ports (Flash_PortA and Flash_PortB) to access the flash
memory consisting of three flash banks. The two ports allow two masters to
access among the three banks in parallel. There are two 2Mbyte banks and one
EEPROM bank. The EEPROM bank is a flash bank that is dedicated for use as
an emulated EEPROM. This device supports 128KB of flash for emulated
EEPROM.
SRAM Level 2 Static RAM There is one slave port to access the on-chip SRAM.
EMAC slaves Ethernet Media Access There are four EMAC slaves:
Controller slave ports
1. EMAC Control Module: this provides an interface between the EMAC and
MDIO modules and the bus masters. It also includes 8KB of RAM to hold
EMAC packet buffer descriptors.
2. EMAC: The EMAC module interfaces to the other devices on the Ethernet
Network using the Media Independent Interface (MII) or Reduced Media
Independent Interface (RMII).
3. Management Data Input / Output (MDIO): The MDIO module is used to
manage the physical layer (PHY) device connected to the EMAC module.
4. Communications Port Programming Interface (CPPI): This is the 8KB of
RAM used to hold the EMAC packet buffer descriptors.
EMIF slaves External Memory Interface There are five EMIF slaves:
slave ports - External SDRAM memory: EMIF chip select 0
- External asynchronous memories: EMIF chip selects 2, 3 and 4
- EMIF module control and status registers
PCRx Peripheral Central Resource The PCR manages the accesses to the peripheral registers and peripheral
controller memories. It provides a global reset for all the peripherals. It also supports the
capability to selectively enable or disable the clock for each peripheral
individually. The PCR also manages the accesses to the system module
registers required to configure the device’s clocks, interrupts, etc. The system
module registers also include status flags for indicating exception conditions –
resets, aborts, errors, interrupts. This device has three PCR modules with each
capable to access different peripherals as shown in the block diagram. The
three PCRs are slaves to the Peripheral Interconnect Subsystem
SDC MMR Safety Diagnostic Checker There are memory mapped status registers to record both the run-time and self-
Memory Map Register Port for test diagnostic of the CPU Interconnect Subsystem. These registers are
CPU Interconnect Subsystem accessed via the SDC MMR slave port in the Peripheral Interconnect
Subsystem.
ADCx Analog-to-Digital Converter The ADC uses the Successive Approximation Register architecture. It features
a selectable 10-bit or 12-bit resolution. The ADC module also includes a RAM
to hold the conversion results. A digital logic wrapper manages accesses to the
control and status registers. There are two ADC modules on this device.
N2HETx New Enhanced High-End The N2HET is an advanced intelligent timer that provides sophisticated timing
Timer functions for real-time applications. The timer is software-controlled, using a
reduced instruction set, with a specialized timer micromachine and an attached
I/O port. The N2HET can be used for pulse width modulated outputs, capture or
compare inputs, or general-purpose I/O.
GIO General-purpose Input/Output The GIO module allows up to 16 terminals to be used as general-purpose Input
or Output. Each of these are also capable of generating an interrupt to the
CPU.
105
SPNU562–May 2014 Architecture
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