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2.1.2 Definitions of Terms
Table 2-1 provides a definition of terms used in the architectural block diagram.
Table 2-1. Definition of Terms
Acronym/Term Full Form Description
ECC Error Correction Code This is a code that is used by the Single Error Correction Double Error
Detection (SECDED) logic inside the two Cortex-R5F processors (CPUs) and
various modules that support ECC. Depending on the memory configuration,
the number of ECC bits may vary. There are 8 bits of ECC for every 64 bits of
data accessed from the CPU level 2 memory such as flash and RAM. CPU's
level 1 cache system consists of instruction cache and data cache and each is
additionally composed of data RAM, tag RAM or dirty RAM. The number of
ECC bits used to protect these RAMs vary. Modules which support ECC
protection on their local RAMs can also employ different number of ECC bits
depending on the RAM's configuration. For example, DMA module use 9 bits of
ECC to protect its local control packet memory.
Lockstep – This is the mode of operation of the dual ARM Cortex-R5F CPUs. The outputs
of the two CPUs are compared on each CPU clock cycle. Any miscompare is
flagged as an error of the highest severity level. In addition to the lockstep
CPUs, the two Vector Interrupt Module (VIM) are also in lockstep.
Cortex-R5F The Cortex-R5F has one AXI-M master port on the CPU Interconnect
CPU Subsystem and another AXI-PP peripheral port on the peripheral Interconnect
Subsystem for low latency access. Each master port is limited to accesses on
the resources attached to the respective interconnect.
uSCU Micro Snooping Control Unit The uSCU which is part of the Cortex-R5 processor system contains an ACP
(Accelerator Coherency Port) interface which provides snoop capabilities on
write-transactions coming from the non-CPU masters. Transactions are
received on the ACP-S slave port, and transmitted on the memory system via
the ACP-M master port. The ACP automatically invalidates the appropriate
Level 1 data-cache lines at the appropriate time, allowing software maintenance
free cache coherency for data in write-through cache regions, as well as non-
cached.
DMA Direct Memory Access The DMA module is used for transferring 8-, 16-, 32- or 64-bit data across the
entire device memory map. The DMA module is one of the bus masters on the
device. That is, it can initiate a read or a write transaction. DMA has two master
ports with DMA_PortA and DMA_PortB. DMA_PortA is connected to the CPU
Interconnect Subsystem and DMA_PortB is connected to the Peripheral
Interconnect Subsystem. DMA can transfer data from resources in CPU
Interconnect Subsystem to resources in the Peripheral Interconnect Subsystem
and vice versa.
DMM Data Modification Module The DMM allows a tool to use the special DMM I/O interface to modify any data
value in any RAM on the device. The modification is done with minimal
interruption to the application execution, and can be used for calibration of
application algorithms. the DMM is also a bus master in this device.
POM Parameter Overlay Module The parameter overlay module redirects accesses to a programmable region in
flash memory (read-only) to a RAM memory, either on-chip or via the external
memory interface (EMIF). This allows a user to evaluate the impact of changing
values of constants stored in the flash memory without actually having to erase
and reprogram the flash. The POM is also a bus master in this device.
DAP Debug Access Port The DAP allows a tool such as a debugger to read from or write to any region in
the device memory map. The DAP is a bus master in this device.
HTUx High-end timer Transfer Unit The HTU is a dedicated transfer unit for the New Enhanced High-End Timer
module. The HTU has a native interface to the N2HET RAM, and is used to
transfer data to / from the N2HET RAM from / to another region in the device
memory map. There is one HTU per N2HET module, so that there are 2 HTU
modules on the device. The HTUx are bus masters in this device.
EMAC Ethernet Media Access The EMAC has a dedicated DMA-type component that is used to transfer data
Controller to / from the EMAC descriptor memory from / to another memory in the device
memory map. This DMA-type component of the EMAC is a bus master in this
device.
PS_SCR_M Peripheral SCR Master Port All transactions to access the resources in the CPU Interconnect Subsystem by
HTUx, EMAC, DMM and DAP will funnel through the PS_SCR_S slave port on
the Peripheral Interconnect Subsystem. The PS_SCR_S slave is then
connected to the PS_SCR_M master port on the CPU Interconnect Subsystem
via a NMPU in between.
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Architecture SPNU562–May 2014
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