Datasheet

HTU1 HTU2
Peripheral Interconnect Subsystem
CRC
1,2
PCR2 PCR3
EMAC Slaves
DCAN1
DCAN2
DCAN3
LIN1/
SCI1
MibSPI4
MDIO
MII
MibSPI1
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
MibSPI2
MIBSPI2_CLK
MIBSPI2_SIMO
MIBSPI2_SOMI
MIBSPI2_nCS[1:0]
MIBSPI2_nENA
MibSPI3
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
MIBSPI4_CLK
MIBSPI4_SIMO
MIBSPI4_SOMI
MIBSPI4_nCS[5:0]
MIBSPI4_nENA
MibSPI5
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[5:0]
MIBSPI5_nENA
LIN1_RX
LIN1_TX
IOMM
PMM
Lockstep
VIMs
RTI
DCC1
DMA
MDCLK
MDIO
MII_RXD[3:0]
MII_RXER
MII_TXD[3:0]
MII_TXEN
MII_TXCLK
MII_RXCLK
MII_CRS
MII_RXDV
MII_COL
EMIF
EMIF_CLK
EMIF_CKE
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[12:0]
EMIF_BA[1:0]
EMIF_DATA [15:0]
EMIF_nDQM[1:0]
EMIF_nOE
EMIF_nWE
EMIF_nRAS
EMIF_nCAS
EMIF_nRW
EMIF_nWAIT
SYS
nPORRST
nRST
ECLK[2:1]
ESM
eQEP
1,2
eQEPxA
eQEPxB
eQEPxS
eQEPxI
eCAP
1..6
eCAP[6:1]
ePWM
1..7
nTZ[3:1]
SYNCO
SYNCI
ePWMxA
ePWMxB
N2HET1 GION2HET2
GIOB[7:0]
GIOA[7:0]
N2HET1[31:0]
N2HET1_PIN_nDIS N2HET2_PIN_nDIS
MibADC 1 MibADC 2
VSSAD
VCCAD
ADREFHI
ADREFLO
NMPU
EMAC
# 2
# 3 # 6
# 1
always on
Core/RAM Core
# 5
Color Legend for
Power Domains
DCAN4
CAN4_RX
CAN4_TX
PCR1
LIN2/
SCI2
LIN2_RX
LIN2_TX
SCI3
SCI3_RX
SCI3_TX
SCI4
SCI4_RX
SCI4_TX
I2C1
I2C1_SDA
I2C1_SCL
I2C2
I2C2_SDA
I2C2_SCL
EMIF
Slave
CPU Interconnect Subsystem
Dual Cortex -R5F
CPUs in lockstep
32kB Icache
& Dcache w /
ECC
POM
4MB Flash
&
128kB
Flash for
EEPROM
Emulation
w/ ECC
512kB
SRAM
w/
ECC
NMPU
NMPU
STC1
EPC
SCM
SYS
DCC2
STC2
DMM
DAP
CCM-
R5F
RTP
nTRST
TMS
TCK
RTCK
TDI
TDO
DMMnENA
DMMSYNC
DMMCLK
DMMDATA[15:0]
TPIU
RTPnENA
RTPSYNC
RTPCLK
RTPDATA[15:0]
ETMDATA[31:0
]
ETMTRACECTL
ETMTRACECLK
ETMTRACECLKIN
MIBSPI5_CLK
N2HET2[31:0]
AD1IN[15:8]/
AD2IN[15:8]
AD2EVT
AD1IN[23:16]/
AD2IN[7:0]
AD1IN[7:0]
AD1EVT
AD2IN[24:16] AD1IN[31:24]
nERROR
uSCU
AD1EXT_ENA
AD1EXT_SEL[4:0]
www.ti.com Family Description
Figure 1-1. Block Diagram
99
SPNU562–May 2014 Introduction
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