Datasheet

www.ti.com Family Description
1.2 Family Description
The RM57Lx family of microcontrollers are cache-based architecture based on the ARM® Cortex™-R5F
Floating Point CPU which offers an efficient 1.66 DMIPS/MHz performance and has configurations which
can run up to 330 MHz providing up to 498 DMIPS. The device supports the little-endian [LE] format.
The RM57Lx has up to 4MB integrated Flash and up to 512KB data RAM configurations with single bit
error correction and double bit error detection. The flash memory on this device is a nonvolatile,
electrically erasable and programmable memory implemented with a 64-bit-wide data bus interface. The
flash operates on a 3.3V supply input (same level as I/O supply) for all read, program and erase
operations. The SRAM operates with a system clock frequency of up to 150 MHz. The SRAM supports
read/write accesses in byte, halfword, and word modes.
The RM57Lx device features peripherals for real-time control-based applications, including two Next
Generation High End Timer (N2HET) timing coprocessors with up to 64 total IO terminals and two 12-bit A
to D converters supporting up to 41 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer
Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to or from main
memory. A Memory Protection Unit (MPU) is built into the HET-TU.
The device has two 12-bit-resolution MibADCs with 41 total channels and 64 words of parity protected
buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are
three separate groupings. Each sequence can be converted once when triggered or configured for
continuous conversion mode.
There are three on die temperature sensors on this device. The temperature measurements of the three
temperature sensors are routed to the MibADC for conversion into digital values. CPU can read out the
digital values and compare with the calibrated temperature value stored in the device's OTP.
The device has multiple communication interfaces: Five MibSPIs, two LINs, two SCIs, four DCANs, two
I
2
C, one Ethernet. The MibSPI provides a convenient method of serial interaction for high-speed
communications between similar shift-register type devices. Data stored in the MibSPI's buffer RAM are
protected with ECC. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in
full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B
protocol standard and uses a serial, multimaster communication protocol that efficiently supports
distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The
DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and
industrial fields) that require reliable serial communication or multiplexed wiring. Messages stored at the
DCAN's RAM are protected with ECC. The Ethernet module supports MII and MDIO interfaces. Transfers
are protected by a standalone Enhanced Memory Protection Unit (NMPU)
The I2C module is a multi-master communication module providing an interface between the
microcontroller and an I2C compatible device via the I2C serial bus. The I2C supports both 100 Kbps and
400 Kbps speeds.
The frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. The FMPLL provides one of the seven possible
clock source inputs to the global clock module (GCM). The GCM module manages the mapping between
the available clock sources and the device clock domains.
The device also has two external clock prescaler (ECP) modules that when enabled, outputs a continuous
external clock on the ECLK1 and ECLK2 terminals. The ECLK frequency is a user-programmable ratio of
the peripheral interface clock (VCLK) frequency. This low frequency output can be monitored externally as
an indicator of the device operating frequency.
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SPNU562–May 2014 Introduction
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