Datasheet

www.ti.com
34-49. Event-Trigger Clear Register (ETCLR) Field Descriptions......................................................... 1815
34-50. PWM-Chopper Control Register (PCCTL) Bit Descriptions ....................................................... 1816
34-51. Digital Compare A Control Register (DCACTL) Field Descriptions............................................... 1818
34-52. Digital Compare Trip Select (DCTRIPSEL) Field Descriptions.................................................... 1819
34-53. Digital Compare Filter Control Register (DCFCTL) Field Descriptions........................................... 1820
34-54. Digital Compare B Control Register (DCBCTL) Field Descriptions............................................... 1821
34-55. Digital Compare Filter Offset Register (DCFOFFSET) Field Descriptions....................................... 1822
34-56. Digital Compare Capture Control Register (DCCAPCTL) Field Descriptions ................................... 1822
34-57. Digital Compare Filter Window Register (DCFWINDOW) Field Descriptions ................................... 1823
34-58. Digital Compare Filter Offset Counter Register (DCFOFFSETCNT) Field Descriptions....................... 1823
34-59. Digital Compare Counter Capture Register (DCCAP) Field Descriptions ....................................... 1824
34-60. Digital Compare Filter Window Counter Register (DCFWINDOWCNT) Field Descriptions ................... 1824
35-1. Encoding of Destination Bits in Trace Mode Packet Format ...................................................... 1828
35-2. Encoding of Status Bits in Trace Mode Packet Format ............................................................ 1828
35-3. Encoding of Write Size in Packet Format ............................................................................ 1828
35-4. Number of Clock Cycles per Packet.................................................................................. 1829
35-5. Pins Used for Data Communication .................................................................................. 1829
35-6. DMM Registers .......................................................................................................... 1832
35-7. DMM Global Control Register (DMMGLBCTRL) Field Descriptions.............................................. 1833
35-8. DMM Interrupt Set Register (DMMINTSET) Field Descriptions................................................... 1835
35-9. DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions ................................................ 1839
35-10. DMM Interrupt Level Register (DMMINTLVL) Field Descriptions................................................. 1844
35-11. DMM Interrupt Flag Register (DMMINTFLG) Field Descriptions.................................................. 1846
35-12. DMM Interrupt Offset 1 Register (DMMOFF1) Field Descriptions ................................................ 1850
35-13. DMM Interrupt Offset 2 Register (DMMOFF1) Field Descriptions ................................................ 1851
35-14. DMM Direct Data Mode Destination Register (DMMDDMDEST) Field Descriptions........................... 1852
35-15. DMM Direct Data Mode Blocksize Register (DMMDDMBL) Field Descriptions................................. 1852
35-16. DMM Direct Data Mode Pointer Register (DMMDDMPT) Field Descriptions ................................... 1853
35-17. DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) Field Descriptions .......................... 1853
35-18. DMM Destination x Region 1 (DMMDESTxREG1) Field Descriptions ........................................... 1854
35-19. DMM Destination x Blocksize 1 (DMMDESTxBL1) Field Descriptions........................................... 1855
35-20. DMM Destination x Region 2 (DMMDESTxREG2) Field Descriptions ........................................... 1856
35-21. DMM Destination x Blocksize 2 (DMMDESTxBL2) Field Descriptions........................................... 1857
35-22. DMM Pin Control 0 (DMMPC0) Field Descriptions ................................................................. 1858
35-23. DMM Pin Control 1 (DMMPC1) Field Descriptions ................................................................. 1859
35-24. DMM Pin Control 2 (DMMPC2) Field Descriptions ................................................................. 1861
35-25. DMM Pin Control 3 (DMMPC3) Field Descriptions ................................................................. 1862
35-26. DMM Pin Control 4 (DMMPC4) Field Descriptions ................................................................. 1863
35-27. DMM Pin Control 5 (DMMPC5) Field Descriptions ................................................................. 1865
35-28. DMM Pin Control 6 (DMMPC6) Field Descriptions ................................................................. 1866
35-29. DMM Pin Control 7 (DMMPC7) Field Descriptions ................................................................. 1868
35-30. DMM Pin Control 8 (DMMPC8) Field Descriptions ................................................................. 1869
36-1. Encoding of RAM Bits in Trace Mode Packet Format.............................................................. 1875
36-2. Encoding of Status Bits in Trace Mode Packet Format ............................................................ 1875
36-3. Encoding of SIZE bits in Trace Mode Packet Format .............................................................. 1875
36-4. Encoding of REG in Trace Mode Packet Format ................................................................... 1875
36-5. Number of Transfers/Packet........................................................................................... 1875
36-6. RTP Signals.............................................................................................................. 1878
36-7. RTP Control Registers.................................................................................................. 1880
92
List of Tables SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated