Datasheet

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31-32. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions.... 1590
31-33. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions .. 1591
31-34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field
Descriptions .............................................................................................................. 1592
31-35. MDIO User Access Register 0 (USERACCESS0) Field Descriptions............................................ 1593
31-36. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions....................................... 1594
31-37. MDIO User Access Register 1 (USERACCESS1) Field Descriptions............................................ 1595
31-38. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions....................................... 1596
31-39. Ethernet Media Access Controller (EMAC) Registers.............................................................. 1597
31-40. Transmit Revision ID Register (TXREVID) Field Descriptions .................................................... 1600
31-41. Transmit Control Register (TXCONTROL) Field Descriptions .................................................... 1600
31-42. Transmit Teardown Register (TXTEARDOWN) Field Descriptions............................................... 1601
31-43. Receive Revision ID Register (RXREVID) Field Descriptions..................................................... 1601
31-44. Receive Control Register (RXCONTROL) Field Descriptions..................................................... 1602
31-45. Receive Teardown Register (RXTEARDOWN) Field Descriptions ............................................... 1602
31-46. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions....................... 1603
31-47. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ..................... 1604
31-48. Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions................................... 1605
31-49. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions............................. 1606
31-50. MAC Input Vector Register (MACINVECTOR) Field Descriptions................................................ 1607
31-51. MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions ................................ 1608
31-52. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions ....................... 1609
31-53. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions...................... 1610
31-54. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ................................... 1611
31-55. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ............................. 1612
31-56. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions......................... 1613
31-57. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions ....................... 1613
31-58. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions..................................... 1614
31-59. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions............................... 1614
31-60. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
Descriptions .............................................................................................................. 1615
31-61. Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions................................... 1617
31-62. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions...................................... 1618
31-63. Receive Maximum Length Register (RXMAXLEN) Field Descriptions........................................... 1618
31-64. Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions ...................................... 1619
31-65. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions...... 1619
31-66. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions ............. 1620
31-67. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions .................... 1620
31-68. MAC Control Register (MACCONTROL) Field Descriptions ...................................................... 1621
31-69. MAC Status Register (MACSTATUS) Field Descriptions.......................................................... 1623
31-70. Emulation Control Register (EMCONTROL) Field Descriptions .................................................. 1625
31-71. FIFO Control Register (FIFOCONTROL) Field Descriptions ...................................................... 1625
31-72. MAC Configuration Register (MACCONFIG) Field Descriptions.................................................. 1626
31-73. Soft Reset Register (SOFTRESET) Field Descriptions ............................................................ 1626
31-74. MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions........................... 1627
31-75. MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions ........................... 1627
31-76. MAC Hash Address Register 1 (MACHASH1) Field Descriptions ................................................ 1628
31-77. MAC Hash Address Register 2 (MACHASH2) Field Descriptions ................................................ 1628
31-78. Back Off Test Register (BOFFTEST) Field Descriptions .......................................................... 1629
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SPNU562–May 2014 List of Tables
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