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30-19. I2C Interrupt Vector Register (I2CIVR) Field Descriptions......................................................... 1514
30-20. Interrupt Codes for INTCODE Bits .................................................................................... 1514
30-21. I2C Extended Mode Register (I2CEMDR) Field Descriptions..................................................... 1515
30-22. I2C Prescale Register (I2CPSC) Field Descriptions................................................................ 1515
30-23. I2C Peripheral ID Register 1 (I2CPID1) Field Descriptions........................................................ 1516
30-24. I2C Peripheral ID Register 2 (I2CPID2) Field Descriptions........................................................ 1516
30-25. I2C DMA Control Register (I2CDMACR) Field Descriptions ...................................................... 1517
30-26. I2C Pin Function Register (I2CPFNC) Field Descriptions ......................................................... 1517
30-27. I2C Pin Direction Register (I2CPDIR) Field Descriptions .......................................................... 1518
30-28. I2C Data Input Register (I2CDIN) Field Descriptions............................................................... 1518
30-29. I2C Data Output Register (I2CDOUT) Field Descriptions.......................................................... 1519
30-30. I2C Data Set Register (I2CDSET) Field Description ............................................................... 1519
30-31. I2C Data Clear Register (I2CDSET) Field Descriptions............................................................ 1520
30-32. I2C Pin Open Drain Register (I2CPDR) Field Descriptions........................................................ 1520
30-33. I2C Pull Disable Register (I2CPDIS) Field Descriptions ........................................................... 1521
30-34. I2C Pull Select Register (I2CPSEL) Field Descriptions ............................................................ 1521
30-35. Input Buffer, Output Buffer, and Pull Control Behavior as GPIO Pins ........................................... 1522
30-36. I2C Pins Slew Rate Select Register (I2CSRS) Field Descriptions................................................ 1522
31-1. EMAC and MDIO Signals for MII Interface .......................................................................... 1529
31-2. EMAC and MDIO Signals for RMII Interface ........................................................................ 1530
31-3. MDIO Multiplexing Control ............................................................................................. 1531
31-4. MII/RMII Multiplexing Control .......................................................................................... 1531
31-5. Ethernet Frame Description............................................................................................ 1532
31-6. Basic Descriptor Description........................................................................................... 1534
31-7. Receive Frame Treatment Summary ................................................................................. 1559
31-8. Middle of Frame Overrun Treatment ................................................................................. 1560
31-9. Emulation Control ....................................................................................................... 1570
31-10. EMAC Control Module Registers...................................................................................... 1571
31-11. EMAC Control Module Revision ID Register (REVID) Field Descriptions ....................................... 1572
31-12. EMAC Control Module Software Reset Register (SOFTRESET)................................................. 1572
31-13. EMAC Control Module Interrupt Control Register (INTCONTROL) .............................................. 1573
31-14. EMAC Control Module Receive Threshold Interrupt Enable Register (C0RXTHRESHEN) ................... 1574
31-15. EMAC Control Module Receive Interrupt Enable Register (C0RXEN)........................................... 1575
31-16. EMAC Control Module Transmit Interrupt Enable Register (C0TXEN) .......................................... 1576
31-17. EMAC Control Module Miscellaneous Interrupt Enable Register (C0MISCEN) ................................ 1577
31-18. EMAC Control Module Receive Threshold Interrupt Status Register (C0RXTHRESHSTAT) ................ 1578
31-19. EMAC Control Module Receive Interrupt Status Register (C0RXSTAT) ........................................ 1579
31-20. EMAC Control Module Transmit Interrupt Status Register (C0TXSTAT) ........................................ 1580
31-21. EMAC Control Module Miscellaneous Interrupt Status Register (C0MISCSTAT) .............................. 1581
31-22. EMAC Control Module Receive Interrupts Per Millisecond Register (C0RXIMAX)............................. 1582
31-23. EMAC Control Module Transmit Interrupts Per Millisecond Register (C0TXIMAX) ............................ 1583
31-24. Management Data Input/Output (MDIO) Registers ................................................................. 1584
31-25. MDIO Revision ID Register (REVID) Field Descriptions ........................................................... 1584
31-26. MDIO Control Register (CONTROL) Field Descriptions ........................................................... 1585
31-27. PHY Acknowledge Status Register (ALIVE) Field Descriptions .................................................. 1586
31-28. PHY Link Status Register (LINK) Field Descriptions ............................................................... 1586
31-29. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions .............. 1587
31-30. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions............. 1588
31-31. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions ..... 1589
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List of Tables SPNU562–May 2014
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