Datasheet

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27-16. SPI Pin Control Register 2 (SPIPC2) Field Descriptions........................................................... 1273
27-17. SPI Pin Control Register 3 (SPIPC3) Field Descriptions........................................................... 1274
27-18. SPI Pin Control Register 4 (SPIPC4) Field Descriptions........................................................... 1275
27-19. SPI Pin Control Register 5 (SPIPC5) Field Descriptions........................................................... 1277
27-20. SPI Pin Control Register 6 (SPIPC6) Field Descriptions........................................................... 1279
27-21. SPI Pin Control Register 7 (SPIPC7) Field Descriptions........................................................... 1280
27-22. SPI Pin Control Register 8 (SPIPC8) Field Descriptions........................................................... 1281
27-23. SPI Transmit Data Register 0 (SPIDAT0) Field Descriptions ..................................................... 1282
27-24. SPI Transmit Data Register 1 (SPIDAT1) Field Descriptions ..................................................... 1283
27-25. SPI Receive Buffer Register (SPIBUF) Field Descriptions ........................................................ 1284
27-26. SPI Emulation Register (SPIEMU) Field Descriptions.............................................................. 1286
27-27. SPI Delay Register (SPIDELAY) Field Descriptions................................................................ 1286
27-28. SPI Default Chip Select Register (SPIDEF) Field Descriptions ................................................... 1289
27-29. SPI Data Format Registers (SPIFMTn) Field Descriptions ........................................................ 1290
27-30. Transfer Group Interrupt Vector 0 (INTVECT0) ..................................................................... 1292
27-31. Transfer Group Interrupt Vector 1 (INTVECT1) ..................................................................... 1293
27-32. SPI Parallel/Modulo Mode Control Register (SPIPMCTRL) Field Descriptions................................. 1295
27-33. Multi-buffer Mode Enable Register (MIBSPIE) Field Descriptions................................................ 1297
27-34. TG Interrupt Enable Set Register (TGITENST) Field Descriptions ............................................... 1298
27-35. TG Interrupt Enable Clear Register (TGITENCR) Field Descriptions ............................................ 1299
27-36. Transfer Group Interrupt Level Set Register (TGITLVST) Field Descriptions................................... 1300
27-37. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions ................................ 1301
27-38. Transfer Group Interrupt Level Clear Register (TGITLVCR) Field Descriptions ................................ 1302
27-39. Tick Count Register (TICKCNT) Field Descriptions ................................................................ 1303
27-40. Last TG End Pointer (LTGPEND) Field Descriptions .............................................................. 1304
27-41. TG Control Registers (TGxCTRL) Field Descriptions .............................................................. 1305
27-42. DMA Channel Control Register (DMAxCTRL) Field Descriptions ................................................ 1308
27-43. MibSPI DMAxCOUNT Register (ICOUNT) Field Descriptions .................................................... 1310
27-44. MibSPI DMA Large Count Register (DMACNTLEN) Field Descriptions ......................................... 1311
27-45. MibSPI Parity/ECC Control Register (PAR_ECC_CTRL) Field Descriptions ................................... 1312
27-46. Parity/ECC Status Register (PAR_ECC_STAT) Field Descriptions .............................................. 1313
27-47. Uncorrectable Parity or Double Bit ECC Error Address Register - RXRAM (UERRADDR1) Field
Descriptions .............................................................................................................. 1314
27-48. Effect of BIG_ENDIAN Port on UERRADDR1[1:0] Bits............................................................ 1315
27-49. Uncorrectable Parity or Double Bit ECC Error Address Register - TXRAM (UERRADDR0) Field
Descriptions .............................................................................................................. 1316
27-50. Effect of BIG_ENDIAN Port on UERRADDR0[1:0] Bits............................................................ 1317
27-51. RXRAM Overrun Buffer Address Register (RXOVRN_BUF_ADDR) Field Descriptions ...................... 1317
27-52. I/O-Loopback Test Control Register (IOLPBKTSTCR) Field Descriptions....................................... 1318
27-53. SPI Extended Prescale Register 1 (EXTENDED_PRESCALE1) Field Descriptions........................... 1320
27-54. SPI Extended Prescale Register 2 (EXTENDED_PRESCALE2) Field Descriptions........................... 1322
27-55. ECC Diagnostic Control Register (ECCDIAG_CTRL) Field Descriptions........................................ 1323
27-56. ECC Diagnostic Status Register (ECCDIAG_STAT) Field Descriptions......................................... 1324
27-57. Single Bit Error Address Register - RXRAM (SBERRADDR1) Field Descriptions ............................. 1325
27-58. Single Bit Error Address Register - TXRAM (SBERRADDR0) Field Descriptions.............................. 1326
27-59. Multi-buffer RAM Register.............................................................................................. 1328
27-60. Multi-buffer RAM Transmit Data Register Field Descriptions...................................................... 1329
27-61. Multi-buffer Receive Buffer Register Field Descriptions............................................................ 1331
28-1. Superfractional Bit Modulation for SCI Mode (Normal Configuration) ........................................... 1350
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SPNU562–May 2014 List of Tables
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