Datasheet

www.ti.com
21-28. SDRAM Refresh Control Register (SDRCR) Field Descriptions ................................................... 807
21-29. Asynchronous n Configuration Register (CEnCFG) Field Descriptions ........................................... 808
21-30. SDRAM Timing Register (SDTIMR) Field Descriptions.............................................................. 809
21-31. SDRAM Self Refresh Exit Timing Register (SDSRETR) Field Descriptions ...................................... 810
21-32. EMIF Interrupt Raw Register (INTRAW) Field Descriptions ........................................................ 811
21-33. EMIF Interrupt Mask Register (INTMSK) Field Descriptions........................................................ 812
21-34. EMIF Interrupt Mask Set Register (INTMSKSET) Field Descriptions.............................................. 813
21-35. EMIF Interrupt Mask Clear Register (INTMSKCLR) Field Descriptions ........................................... 814
21-36. Page Mode Control Register (PMCR) Field Descriptions ........................................................... 815
21-37. SR Field Value For the EMIF to K4S641632H-TC(L)70 Interface ................................................. 816
21-38. SDTIMR Field Calculations for the EMIF to K4S641632H-TC(L)70 Interface .................................... 818
21-39. RR Calculation for the EMIF to K4S641632H-TC(L)70 Interface .................................................. 819
21-40. RR Calculation for the EMIF to K4S641632H-TC(L)70 Interface .................................................. 819
21-41. SDCR Field Values For the EMIF to K4S641632H-TC(L)70 Interface ............................................ 820
21-42. AC Characteristics for a Read Access................................................................................. 821
21-43. AC Characteristics for a Write Access ................................................................................. 821
22-1. ADC Look-Up Table Field Descriptions................................................................................ 838
22-2. Calibration Reference Voltages......................................................................................... 848
22-3. Self-Test Reference Voltages........................................................................................... 851
22-4. Determination of ADC Input Channel Condition ...................................................................... 852
22-5. Output Buffer and Pull Control Behavior for ADxEVT as GPIO Pins .............................................. 856
22-6. ADC Registers ............................................................................................................ 857
22-7. ADC Reset Control Register (ADRSTCR) Field Descriptions ...................................................... 859
22-8. ADC Operating Mode Control Register (ADOPMODECR) Field Descriptions ................................... 859
22-9. ADC Clock Control Register (ADCLOCKCR) Field Descriptions................................................... 861
22-10. ADC Calibration Mode Control Register (ADCALCR) Field Descriptions ........................................ 862
22-11. ADC Event Group Operating Mode Control Register (ADEVMODECR) Field Descriptions.................... 864
22-12. ADC Group1 Operating Mode Control Register (ADG1MODECR) Field Descriptions .......................... 867
22-13. ADC Group 2 Operating Mode Control Register (ADG2MODECR) Field Descriptions ......................... 870
22-14. ADC Event Group Trigger Source Select Register (ADEVSRC) Field Descriptions............................. 872
22-15. ADC Group1 Trigger Source Select Register (ADG1SRC) Field Descriptions ................................... 873
22-16. ADC Group2 Trigger Source Select Register (ADG2SRC) Field Descriptions ................................... 874
22-17. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) Field Descriptions ...................... 875
22-18. ADC Group1 Interrupt Enable Control Register (ADG1INTENA) Field Descriptions ............................ 876
22-19. ADC Group2 Interrupt Enable Control Register (ADG2INTENA) Field Descriptions ............................ 877
22-20. ADC Event Group Interrupt Flag Register (ADEVINTFLG) Field Descriptions ................................... 878
22-21. ADC Group1 Interrupt Flag Register (ADG1INTFLG) Field Descriptions ......................................... 879
22-22. ADC Group2 Interrupt Flag Register (ADG2INTFLG) Field Descriptions ......................................... 880
22-23. ADC Event Group Threshold Interrupt Control Register (ADEVTHRINTCR) Field Descriptions .............. 881
22-24. ADC Group1 Threshold Interrupt Control Register (ADG1THRINTCR) Field Descriptions..................... 881
22-25. ADC Group2 Threshold Interrupt Control Register (ADG2THRINTCR) Field Descriptions..................... 882
22-26. ADC Event Group DMA Control Register (ADEVDMACR) Field Descriptions ................................... 883
22-27. ADC Group1 DMA Control Register (ADG1DMACR) Field Descriptions ......................................... 885
22-28. ADC Group2 DMA Control Register (ADG2DMACR) Field Descriptions ......................................... 887
22-29. ADC Results Memory Configuration Register (ADBNDCR) Field Descriptions .................................. 889
22-30. ADC Results Memory Size Configuration Register (ADBNDEND) Field Descriptions .......................... 890
22-31. ADC Event Group Sampling Time Configuration Register (ADEVSAMP) Field Descriptions .................. 891
22-32. ADC Group1 Sampling Time Configuration Register (ADG1SAMP) Field Descriptions ........................ 891
22-33. ADC Group2 Sampling Time Configuration Register (ADG2SAMP) Field Descriptions ........................ 892
79
SPNU562–May 2014 List of Tables
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated