Datasheet

www.ti.com
20-40. HBC Interrupt Enable Set Register (HBCINTENAS) Field Descriptions .......................................... 726
20-41. HBC Interrupt Enable Reset Register (HBCINTENAR) Field Descriptions ....................................... 726
20-42. BTC Interrupt Enable Reset Register (BTCINTENAS) Field Descriptions ........................................ 727
20-43. BTC Interrupt Enable Reset Register (BTCINTENAR) Field Descriptions ........................................ 727
20-44. Global Interrupt Flag Register (GINTFLAG) Field Descriptions .................................................... 728
20-45. FTC INTERRUPT FLAG Register (FTCFLAG) Field Descriptions................................................. 728
20-46. LFS Interrupt Flag Register (LFSFLAG) Field Descriptions......................................................... 729
20-47. HBC Interrupt Flag Register (HBCFLAG) Field Descriptions ....................................................... 729
20-48. BTC Interrupt Flag Register (BTCFLAG) Field Descriptions........................................................ 730
20-49. BER Interrupt Flag Register (BERFLAG) Field Descriptions ....................................................... 730
20-50. FTCA Interrupt Channel Offset Register (FTCAOFFSET) Field Descriptions .................................... 731
20-51. LFSA Interrupt Channel Offset Register (LFSAOFFSET) Field Descriptions..................................... 731
20-52. HBCA Interrupt Channel Offset Register (HBCAOFFSET) Field Descriptions ................................... 732
20-53. BTCA Interrupt Channel Offset Register (BTCAOFFSET) Field Descriptions.................................... 732
20-54. BERA Interrupt Channel Offset Register (BERAOFFSET) Field Descriptions ................................... 733
20-55. FTCB Interrupt Channel Offset Register (FTCBOFFSET) Field Descriptions .................................... 733
20-56. LFSB Interrupt Channel Offset Register (LFSBOFFSET) Field Descriptions..................................... 734
20-57. HBCB Interrupt Channel Offset Register (HBCBOFFSET) Field Descriptions ................................... 734
20-58. BTCB Interrupt Channel Offset Register (BTCBOFFSET) Field Descriptions.................................... 735
20-59. BERB Interrupt Channel Offset Register (BERBOFFSET) Field Descriptions ................................... 735
20-60. Port Control Register (PTCRL) Field Descriptions ................................................................... 736
20-61. RAM Test Control Register (RTCTRL) Field Descriptions .......................................................... 737
20-62. Debug Control Register (DCTRL) Field Descriptions ................................................................ 738
20-63. Watch Point Register (WPR) Field Descriptions...................................................................... 739
20-64. Watch Mask Register (WMR) Field Descriptions..................................................................... 739
20-65. FIFO A Active Channel Source Address Register (FAACSADDR) Field Descriptions .......................... 740
20-66. FIFO A Active Channel Destination Address Register (PBACDADDR) Field Descriptions..................... 740
20-67. Port B Active Channel Transfer Count Register (PBACTC) Field Descriptions .................................. 740
20-68. FIFO B Active Channel Source Address Register (FBACSADDR) Field Descriptions .......................... 741
20-69. FIFO B Active Channel Destination Address Register (FBACDADDR) Field Descriptions ..................... 741
20-70. FIFO B Active Channel Transfer Count Register (FBACTC) Field Descriptions ................................. 741
20-71. ECC Control Register (DMAPECR) Field Descriptions.............................................................. 742
20-72. DMA ECC Error Address Register (DMAPAR) Field Descriptions ................................................. 743
20-73. DMA Memory Protection Control Register 1 (DMAMPCTRL1) Field Descriptions............................... 744
20-74. DMA Memory Protection Status Register 1 (DMAMPST1) Field Descriptions ................................... 746
20-75. DMA Memory Protection Region 0 Start Address Register (DMAMPR0S) Field Descriptions................. 747
20-76. DMA Memory Protection Region 0 End Address Register (DMAMPR0E)] Field Descriptions ................. 747
20-77. DMA Memory Protection Region 1 Start Address Register (DMAMPR1S) Field Descriptions................. 748
20-78. DMA Memory Protection Region 1 End Address Register (DMAMPR1E) Field Descriptions.................. 748
20-79. DMA Memory Protection Region 2 Start Address Register (DMAMPR2S) Field Descriptions................. 749
20-80. DMA Memory Protection Region 2 End Address Register (DMAMPR2E) Field Descriptions.................. 749
20-81. DMA Memory Protection Region 3 Start Address Register (DMAMPR3S) Field Descriptions................. 750
20-82. DMA Memory Protection Region 3 End Address Register (DMAMPR3E) Field Descriptions.................. 750
20-83. DMA Memory Protection Control Register 2 (DMAMPCTRL2) Field Descriptions............................... 751
20-84. DMA Memory Protection Status Register 2 (DMAMPST2) Field Descriptions ................................... 753
20-85. DMA Memory Protection Region 4 Start Address Register (DMAMPR4S) Field Descriptions................. 754
20-86. DMA Memory Protection Region 4 End Address Register (DMAMPR4E)] Field Descriptions ................. 754
20-87. DMA Memory Protection Region 1 Start Address Register (DMAMPR1S) Field Descriptions................. 755
20-88. DMA Memory Protection Region 1 End Address Register (DMAMPR1E) Field Descriptions.................. 755
77
SPNU562–May 2014 List of Tables
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated