Datasheet
www.ti.com
18-4. CRC Control Registers................................................................................................... 621
18-5. CRC Global Control Register 0 (CRC_CTRL0) Field Descriptions ................................................ 622
18-6. CRC Global Control Register 1 (CRC_CTRL1) Field Descriptions ................................................ 622
18-7. CRC Global Control Register 2 (CRC_CTRL2) Field Descriptions ................................................ 623
18-8. CRC Interrupt Enable Set Register (CRC_INTS) Field Descriptions .............................................. 624
18-9. CRC Interrupt Enable Reset Register (CRC_INTR) Field Descriptions ........................................... 626
18-10. CRC Interrupt Status Register (CRC_STATUS) Field Descriptions ............................................... 628
18-11. CRC Interrupt Offset (CRC_INT_OFFSET_REG) Field Descriptions ............................................. 630
18-12. CRC Busy Register (CRC_BUSY) Field Descriptions ............................................................... 631
18-13. CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1) Field Descriptions......................... 631
18-14. CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) Field Descriptions.......................... 632
18-15. CRC Current Sector Register 1 (CRC_CURSEC_REG1) Field Descriptions .................................... 632
18-16. CRC Channel 1 Watchdog Timeout Preload Register A (CRC_WDTOPLD1) Field Descriptions............. 633
18-17. CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1) Field Descriptions ....... 633
18-18. Channel 1 PSA Signature Low Register (PSA_SIGREGL1) Field Descriptions ................................. 634
18-19. Channel 1 PSA Signature High Register (PSA_SIGREGH1) Field Descriptions ................................ 634
18-20. Channel 1 CRC Value Low Register (CRC_REGL1) Field Descriptions.......................................... 634
18-21. Channel 1 CRC Value High Register (CRC_REGH1) Field Descriptions......................................... 635
18-22. Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1) Field Descriptions ................... 635
18-23. Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1) Field Descriptions .................. 635
18-24. Channel 1 Raw Data Low Register (RAW_DATAREGL1) Field Descriptions.................................... 636
18-25. Channel 1 Raw Data High Register (RAW_DATAREGH1) Field Descriptions................................... 636
18-26. CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2) Field Descriptions......................... 636
18-27. CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) Field Descriptions.......................... 637
18-28. CRC Current Sector Register 2 (CRC_CURSEC_REG2) Field Descriptions .................................... 637
18-29. CRC Channel 2 Watchdog Timeout Preload Register A (CRC_WDTOPLD2) Field Descriptions............. 638
18-30. CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2) Field Descriptions....... 638
18-31. Channel 2 PSA Signature Low Register (PSA_SIGREGL2) Field Descriptions ................................. 639
18-32. Channel 2 PSA Signature High Register (PSA_SIGREGH2) Field Descriptions ................................ 639
18-33. Channel 2 CRC Value Low Register (CRC_REGL2) Field Descriptions.......................................... 639
18-34. Channel 2 CRC Value High Register (CRC_REGH2) Field Descriptions......................................... 640
18-35. Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2) Field Descriptions ................... 640
18-36. Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2) Field Descriptions .................. 640
18-37. Channel 2 Raw Data Low Register (RAW_DATAREGL2) Field Descriptions.................................... 641
18-38. Channel 2 Raw Data High Register (RAW_DATAREGH2) Field Descriptions................................... 641
19-1. ECC Syndrome Table.................................................................................................... 653
19-2. ECC Error Bits for Syndrome Decode ................................................................................. 653
19-3. CPU Reads - Address Bit 10 Selects Between Normal Data and ECC Bits...................................... 654
19-4. CPU Writes - Address Bit 10 Selects Between Normal Data and ECC Bits...................................... 654
19-5. VIM Control Registers.................................................................................................... 660
19-6. Interrupt Vector Table ECC Status Register (ECCSTAT) Field Descriptions..................................... 661
19-7. Interrupt Vector Table ECC Control Register (ECCCTL) Field Descriptions ..................................... 662
19-8. Uncorrectable Error Address Register (UERRADDR) Field Descriptions......................................... 663
19-9. Fallback Vector Address Register (FBVECADDR) Field Descriptions............................................. 663
19-10. Single Bit Error Address Register (SBERRADDR) Field Descriptions............................................. 664
19-11. Interrupt Dispatch......................................................................................................... 664
19-12. IRQ Index Offset Vector Register (IRQINDEX) Field Descriptions................................................. 665
19-13. FIQ Index Offset Vector Register (FIQINDEX) Field Descriptions ................................................. 665
19-14. FIQ/IRQ Program Control Registers (FIRQPR) Field Descriptions ............................................... 666
75
SPNU562–May 2014 List of Tables
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated