Datasheet
Copyright © 2014–2016, Texas Instruments IncorporatedTerminal Configuration and Functions
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RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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4.2.1.13 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-13. ZWT Multibuffered Serial Peripheral Interface Modules (MibSPI)
Terminal
Signal Type
Default Pull
State
Pull Type
Output Buffer
Drive Strength
Description
Signal Name
337
ZWT
MIBSPI1CLK F18 I/O Pullup Programmable, 20 µA 8mA MibSPI1 clock, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 R2 I/O Pullup Programmable, 20 >µA 8mA MibSPI1 chip select, or GIO
MIBSPI1NCS[1]/MII_COL/N2HET1[17]/eQEP1S F3 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 chip select, or GIO
MIBSPI1NCS[2]/MDIO /N2HET1[19] G3 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 chip select, or GIO
MIBSPI1NCS[3]/N2HET1[21]/nTZ1_3 J3 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 chip select, or GIO
MIBSPI1NCS[4] U10 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 chip select, or GIO
N2HET1[15]/MIBSPI1NCS[4]/N2HET2[22]/ECAP1 N1(1)
MIBSPI1NCS[5] U9 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 chip select, or GIO
N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] P1(1)
MIBSPI1NENA/MII_RXD[2]/N2HET1[23]/ECAP4 G19 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI1 enable, or GIO
MIBSPI1SIMO[0] F19 I/O Pullup Programmable, 20 µA 8mA MibSPI1 slave-in master-out, or GIO
N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] E18 I/O Pulldown Programmable, 20 µA 8mA MibSPI1 slave-in master-out, or GIO
MIBSPI1SOMI[0] G18 I/O Pullup Programmable, 20 µA 8mA MibSPI1 slave-out master-in, or GIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2]/ECAP6 R2 I/O Pullup Programmable, 20 µA 8mA MibSPI1 slave-out master-in, or GIO
N2HET2[3]/MIBSPI2CLK E2 I/O Pulldown Programmable, 20 µA 8mA MibSPI2 clock, or GIO
N2HET2[7]/MIBSPI2NCS[0] N3 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI2 chip select, or GIO
N2HET2[12]/MIBSPI2NENA/MIBSPI2NCS[1] D3 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI2 chip select, or GIO
N2HET2[12]/MIBSPI2NENA/MIBSPI2NCS[1] D3 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI2 enable, or GIO
N2HET2[14]/MIBSPI2SIMO D1 I/O Pulldown Programmable, 20 µA 8mA MibSPI2 slave-in master-out, or GIO
N2HET2[13]/MIBSPI2SOMI D2 I/O Pulldown Programmable, 20 µA 8mA MibSPI2 slave-out master-in, or GIO
MIBSPI3CLK/AD1EXT_SEL[1]/eQEP1A V9 I/O Pullup Programmable, 20 µA 8mA MibSPI3 clock, or GIO
MIBSPI3NCS[0]/AD2EVT/eQEP1I V10 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
MIBSPI3NCS[1]/MDCLK/N2HET1[25] V5 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
MIBSPI3NCS[2]/I2C1_SDA/N2HET1[27] /nTZ1_2 B2 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
MIBSPI3NCS[3]/I2C1_SCL/N2HET1[29] /nTZ1_1 C3 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/ePWM1SYNCO E3 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/eQEP1B W9 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 chip select, or GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/eQEP1B W9 I/O Pullup Programmable, 20 µA 2mA ZD MibSPI3 enable, or GIO
MIBSPI3SIMO/AD1EXT_SEL[0]/ECAP3 W8 I/O Pullup Programmable, 20 µA 8mA MibSPI3 slave-in master-out, or GIO
MIBSPI3SOMI/AD1EXT_ENA/ECAP2 V8 I/O Pullup Programmable, 20 µA 8mA MibSPI3 slave-out master-in, or GIO
N2HET1[0]/MIBSPI4CLK/ePWM2B K18 I/O Pulldown Programmable, 20 µA 8mA MibSPI4 clock, or GIO
N2HET1[3]/MIBSPI4NCS[0]/N2HET2[10]/eQEP2B U1 I/O Pulldown Programmable, 20 µA 2mA ZD MibSPI4 chip select, or GIO