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2-97. Peripheral Protection Clear Register 3 (PPROTCLR3) Field Descriptions ....................................... 215
2-98. Peripheral Memory Power-Down Set Register 0 (PCSPWRDWNSET0) Field Descriptions ................... 215
2-99. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNSET1) Field Descriptions ................... 216
2-100. Peripheral Memory Power-Down Clear Register 0 (PCSPWRDWNCLR0) Field Descriptions................. 216
2-101. Peripheral Memory Power-Down Set Register 1 (PCSPWRDWNCLR1) Field Descriptions ................... 217
2-102. Peripheral Power-Down Set Register 0 (PSPWRDWNSET0) Field Descriptions................................ 218
2-103. Peripheral Power-Down Set Register 1 (PSPWRDWNSET1) Field Descriptions................................ 219
2-104. Peripheral Power-Down Set Register 2 (PSPWRDWNSET2) Field Descriptions................................ 219
2-105. Peripheral Power-Down Set Register 3 (PSPWRDWNSET3) Field Descriptions................................ 220
2-106. Peripheral Power-Down Clear Register 0 (PSPWRDWNCLR0) Field Descriptions ............................. 220
2-107. Peripheral Power-Down Clear Register 1 (PSPWRDWNCLR1) Field Descriptions ............................. 221
2-108. Peripheral Power-Down Clear Register 2 (PSPWRDWNCLR2) Field Descriptions ............................. 221
2-109. Peripheral Power-Down Clear Register 3 (PSPWRDWNCLR3) Field Descriptions ............................. 222
2-110. Debug Frame Powerdown Set Register (PDPWRDWNSET) Field Descriptions ................................ 222
2-111. Debug Frame Powerdown Clear Register (PDPWRDWNCLR) Field Descriptions .............................. 223
2-112. MasterID Protection Write Enable Register (MSTIDWRENA) Field Descriptions................................ 223
2-113. MasterID Enable Register (MSTIDENA) Field Descriptions ........................................................ 224
2-114. MasterID Diagnostic Control Register (MSTIDDIAGCTRL) Field Descriptions................................... 225
2-115. Peripheral Frame 0 MasterID Protection Register_L (PS0MSTID_L) Field Descriptions ....................... 226
2-116. Peripheral Frame 0 MasterID Protection Register_H (PS0MSTID_H) Field Descriptions ...................... 227
2-117. Peripheral Frame n MasterID Protection Register_L/H (PSnMSTID_L/H) Field Descriptions.................. 228
2-118. Privileged Peripheral Frame 0 MasterID Protection Register_L (PPS0MSTID_L) Field Descriptions......... 229
2-119. Privileged Peripheral Frame 0 MasterID Protection Register_H (PPS0MSTID_H) Field Description ......... 230
2-120. Privileged Peripheral Frame n MasterID Protection Register_L/H (PPSnMSTID_L/H) Field Descriptions ... 231
2-121. Privileged Peripheral Extended Frame 0 MasterID Protection Register_L (PPSE0MSTID_L) Field
Descriptions ............................................................................................................... 232
2-122. Privileged Peripheral Extended Frame 0 MasterID Protection Register_H (PPSE0MSTID_H) Field
Descriptions ............................................................................................................... 233
2-123. Privileged Peripheral Extended Frame n MasterID Protection Register_L/H (PPSEnMSTID_L/H) Field
Descriptions ............................................................................................................... 234
2-124. Peripheral Memory Frame MasterID Protection Register (PCSnMSTID) Field Descriptions ................... 235
2-125. Privileged Peripheral Memory Frame MasterID Protection Register (PPCSnMSTID) Field Descriptions .... 236
3-1. SCM Registers ............................................................................................................ 245
3-2. SCM REVID Register (SCMREVID) Field Descriptions ............................................................. 245
3-3. SCM Control Register (SCMCNTRL) Field Descriptions ............................................................ 246
3-4. SCM Compare Threshold Counter Register (SCMTHRESHOLD) Field Descriptions........................... 247
3-5. SCM Initiator Error0 Status Register (SCMIAERR0STAT) Field Descriptions ................................... 248
3-6. SCM Initiator Error1 Status Register (SCMIAERR1STAT) Field Descriptions ................................... 248
3-7. SCM Initiator Active Status Register (SCMIASTAT) Field Descriptions........................................... 249
3-8. SCM Target Active Status Register (SCMTASTAT) Field Descriptions........................................... 249
4-1. Bus Master / Slave Connectivity for Peripheral Interconnect Subsystem ......................................... 251
4-2. CPU Interconnect Subsystem SDC Register Bit Field Mapping.................................................... 252
4-3. Bus Master / Slave Connectivity for CPU Interconnect Subsystem................................................ 253
4-4. SCM Register Bit Mapping .............................................................................................. 256
4-5. SDC MMR Registers ..................................................................................................... 257
4-6. SDC Status Register (SDC_STATUS) Field Descriptions........................................................... 258
4-7. SDC Control Register (SDC_CONTROL) Field Descriptions ....................................................... 259
4-8. Error Generic Parity Register (ERR_GENERIC_PARITY) Field Descriptions.................................... 259
4-9. Error Unexpected Transaction Register (ERR_UNEXPECTED_TRANS) Field Descriptions .................. 260
4-10. Error Transaction ID Register (ERR_TRANS_ID) Field Descriptions.............................................. 260
68
List of Tables SPNU562–May 2014
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