Datasheet

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35-21. DMM Destination x Blocksize 2 (DMMDESTxBL2) [offset = 38h, 48h, 58h, 68h] .............................. 1857
35-22. DMM Pin Control 0 (DMMPC0) [offset = 6Ch] ...................................................................... 1858
35-23. DMM Pin Control 1 (DMMPC1) [offset = 70h] ....................................................................... 1859
35-24. DMM Pin Control 2 (DMMPC2) [offset = 74h] ....................................................................... 1861
35-25. DMM Pin Control 3 (DMMPC3) [offset = 78h] ....................................................................... 1862
35-26. DMM Pin Control 4 (DMMPC4) [offset = 7Ch] ...................................................................... 1863
35-27. DMM Pin Control 5 (DMMPC5) [offset = 80h] ....................................................................... 1865
35-28. DMM Pin Control 6 (DMMPC6) [offset = 84h] ....................................................................... 1866
35-29. DMM Pin Control 7 (DMMPC7) [offset = 88h] ....................................................................... 1868
35-30. DMM Pin Control 8 (DMMPC8) [offset = 8Ch] ...................................................................... 1869
36-1. RAM Trace Port Module Block Diagram ............................................................................. 1873
36-2. Packet Format Trace Mode for RAM Locations..................................................................... 1874
36-3. Packet Format Trace Mode for Peripheral Locations .............................................................. 1874
36-4. Packet Format in Direct Data Mode .................................................................................. 1876
36-5. Example for Trace Region Setup ..................................................................................... 1877
36-6. FIFO Overflow Handling................................................................................................ 1878
36-7. RTP Packet Transfer with Sync Signal............................................................................... 1879
36-8. Packet Format in Trace Mode ......................................................................................... 1879
36-9. RTP Global Control Register (RTPGLBCTRL) (offset = 00h) ..................................................... 1881
36-10. RTP Trace Enable Register (RTPTRENA) (offset = 04h).......................................................... 1884
36-11. RTP Global Status Register (RTPGSR) (offset = 08h)............................................................. 1886
36-12. RTP RAM 1 Trace Region Registers (RTPRAM1REGn) (offset = 0Ch and 10h) .............................. 1888
36-13. RTP RAM 2 Trace Region Registers (RTPRAM2REGn) (offset = 14h and 18h)............................... 1889
36-14. RTP RAM 3 Trace Region Registers (RTPRAM3REGn) (offset = 1Ch and 20h) .............................. 1890
36-15. RTP Peripheral Trace Region Registers (RTPPERREGn) (offset = 24h and 28h)............................. 1892
36-16. RTP Direct Data Mode Write Register (RTPDDMW) (offset = 2Ch) ............................................. 1893
36-17. RTP Pin Control 0 Register (RTPPC0) (offset = 34h).............................................................. 1894
36-18. RTP Pin Control 1 Register (RTPPC1) (offset = 38h).............................................................. 1895
36-19. RTP Pin Control 2 Register (RTPPC2) (offset = 3Ch) ............................................................. 1896
36-20. RTP Pin Control 3 Register (RTPPC3) (offset = 40h).............................................................. 1897
36-21. RTP Pin Control 4 Register (RTPPC4) (offset = 44h).............................................................. 1898
36-22. RTP Pin Control 5 Register (RTPPC5) (offset = 48h).............................................................. 1899
36-23. RTP Pin Control 6 Register (RTPPC6) (offset = 4Ch) ............................................................. 1900
36-24. RTP Pin Control 7 Register (RTPPC7) (offset = 50h).............................................................. 1902
36-25. RTP Pin Control 8 Register (RTPPC8) (offset = 54h).............................................................. 1903
37-1. eFuse Self Test Flow Chart............................................................................................ 1907
37-2. EFC Boundary Control Register (EFCBOUND) [offset = 1Ch].................................................... 1908
37-3. EFC Pins Register (EFCPINS) [offset = 2Ch] ...................................................................... 1910
37-4. EFC Error Status Register (EFCERRSTAT) [offset = 3Ch]........................................................ 1911
37-5. EFC Self Test Cycles Register (EFCSTCY) [offset = 48h] ........................................................ 1911
37-6. EFC Self Test Cycles Register (EFCSTSIG) [offset = 4Ch] ....................................................... 1912
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SPNU562–May 2014 List of Figures
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