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34-72. Action-Qualifier Software Force Register (AQSFRC) [offset = 1A] ............................................... 1796
34-73. Action-Qualifier Output B Control Register (AQCTLB) [offset = 18h] ............................................ 1797
34-74. Action-Qualifier Continuous Software Force Register (AQCSFRC) [offset = 1Ch] ............................. 1798
34-75. Dead-Band Generator Control Register (DBCTL) [offset = 1Eh] ................................................. 1799
34-76. Dead-Band Generator Falling Edge Delay Register (DBFED) [offset = 22h] ................................... 1801
34-77. Dead-Band Generator Rising Edge Delay Register (DBRED) [offset = 20h].................................... 1801
34-78. Trip Zone Digital Compare Event Select Register (TZDCSEL) [offset = 26h]................................... 1802
34-79. Trip-Zone Select Register (TZSEL) [offset = 24h] .................................................................. 1803
34-80. Trip-Zone Enable Interrupt Register (TZEINT) [offset = 2Ah] ..................................................... 1805
34-81. Trip-Zone Control Register (TZCTL) [offset = 28h] ................................................................. 1806
34-82. Trip-Zone Clear Register (TZCLR) [offset = 2Eh]................................................................... 1807
34-83. Trip-Zone Flag Register (TZFLG) [offset = 2Ch] .................................................................... 1808
34-84. Trip-Zone Force Register (TZFRC) [offset = 30h] .................................................................. 1809
34-85. Event-Trigger Selection Register (ETSEL) [offset = 32h].......................................................... 1810
34-86. Event-Trigger Flag Register (ETFLG) [offset = 36h]................................................................ 1811
34-87. Event-Trigger Prescale Register (ETPS) [offset = 34h] ............................................................ 1812
34-88. Event-Trigger Force Register (ETFRC) [offset = 3Ah] ............................................................. 1814
34-89. Event-Trigger Clear Register (ETCLR) [offset = 38h] .............................................................. 1815
34-90. PWM-Chopper Control Register (PCCTL) [offset = 3Ch........................................................... 1816
34-91. Digital Compare A Control Register (DCACTL) [offset = 62h] .................................................... 1818
34-92. Digital Compare Trip Select (DCTRIPSEL) [offset = 60h] ......................................................... 1819
34-93. Digital Compare Filter Control Register (DCFCTL) [offset = 66h] ................................................ 1820
34-94. Digital Compare B Control Register (DCBCTL) [offset = 64h] .................................................... 1821
34-95. Digital Compare Filter Offset Register (DCFOFFSET) [offset = 6Ah] ............................................ 1822
34-96. Digital Compare Capture Control Register (DCCAPCTL) [offset = 68h]......................................... 1822
34-97. Digital Compare Filter Window Register (DCFWINDOW) [offset = 6Eh] ........................................ 1823
34-98. Digital Compare Filter Offset Counter Register (DCFOFFSETCNT) [offset = 6Ch] ............................ 1823
34-99. Digital Compare Counter Capture Register (DCCAP) [offset = 72h] ............................................. 1824
34-100. Digital Compare Filter Window Counter Register (DCFWINDOWCNT) [offset = 70h] ....................... 1824
35-1. DMM Block Diagram.................................................................................................... 1826
35-2. Trace Mode Packet Format ............................................................................................ 1828
35-3. Direct Data Mode Packet Format ..................................................................................... 1828
35-4. Packet Sync Signal Example .......................................................................................... 1830
35-5. Example Single Packet Transmission ................................................................................ 1830
35-6. Interrupt Structure ....................................................................................................... 1831
35-7. DMM Global Control Register (DMMGLBCTRL) [offset = 00h] ................................................... 1833
35-8. DMM Interrupt Set Register (DMMINTSET) [offset = 04h]......................................................... 1835
35-9. DMM Interrupt Clear Register (DMMINTCLR) [offset = 08h] ...................................................... 1839
35-10. DMM Interrupt Level Register (DMMINTLVL) [offset = 0Ch] ...................................................... 1844
35-11. DMM Interrupt Flag Register (DMMINTFLG) [offset = 10h] ....................................................... 1846
35-12. DMM Interrupt Offset 1 Register (DMMOFF1) [offset = 14h]...................................................... 1850
35-13. DMM Interrupt Offset 2 Register (DMMOFF2) [offset = 18h]...................................................... 1851
35-14. DMM Direct Data Mode Destination Register (DMMDDMDEST) [offset = 1Ch]................................ 1852
35-15. DMM Direct Data Mode Blocksize Register (DMMDDMBL) [offset = 20h] ...................................... 1852
35-16. DMM Direct Data Mode Pointer Register (DMMDDMPT) [offset = 24h] ......................................... 1853
35-17. DMM Direct Data Mode Interrupt Pointer Register (DMMINTPT) [offset = 28h]................................ 1853
35-18. DMM Destination x Region 1 (DMMDESTxREG1) [offset = 2Ch, 3Ch, 4Ch, 5Ch]............................. 1854
35-19. DMM Destination x Blocksize 1 (DMMDESTxBL1) [offset = 30h, 40h, 50h, 60h] .............................. 1855
35-20. DMM Destination x Region 2 (DMMDESTxREG2) [offset = 34h, 44h, 54h, 64h] .............................. 1856
64
List of Figures SPNU562–May 2014
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