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EPWMxB — Complementary .......................................................................................... 1743
34-26. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low........................................................................................................................ 1744
34-27. Dead_Band Submodule ................................................................................................ 1745
34-28. Configuration Options for the Dead-Band Submodule ............................................................. 1746
34-29. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%).................................................. 1748
34-30. PWM-Chopper Submodule ............................................................................................ 1750
34-31. PWM-Chopper Submodule Operational Details..................................................................... 1751
34-32. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only............................... 1751
34-33. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses...... 1752
34-34. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses..................................................................................................................... 1753
34-35. Trip-Zone Submodule................................................................................................... 1754
34-36. Trip-Zone Submodule Mode Control Logic .......................................................................... 1758
34-37. Trip-Zone Submodule Interrupt Logic................................................................................. 1759
34-38. Event-Trigger Submodule .............................................................................................. 1760
34-39. Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion....................................... 1761
34-40. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs....................................... 1762
34-41. Event-Trigger Interrupt Generator..................................................................................... 1764
34-42. Event-Trigger SOCA Pulse Generator ............................................................................... 1764
34-43. Event-Trigger SOCB Pulse Generator ............................................................................... 1765
34-44. Digital-Compare Submodule High-Level Block Diagram........................................................... 1765
34-45. DCAEVT1 Event Triggering............................................................................................ 1768
34-46. DCAEVT2 Event Triggering............................................................................................ 1768
34-47. DCBEVT1 Event Triggering............................................................................................ 1769
34-48. DCBEVT2 Event Triggering............................................................................................ 1769
34-49. Event Filtering ........................................................................................................... 1770
34-50. Blanking Window Timing Diagram .................................................................................... 1771
34-51. Simplified ePWM Module............................................................................................... 1772
34-52. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave ..................................... 1773
34-53. Control of Four Buck Stages. Here F
PWM1
≠ F
PWM2
≠ F
PWM3
≠ F
PWM4
.................................................. 1774
34-54. Buck Waveforms for (Note: Only three bucks shown here) ....................................................... 1775
34-55. Control of Four Buck Stages. (Note: F
PWM2
= N x F
PWM1
)............................................................ 1777
34-56. Buck Waveforms for (Note: F
PWM2
= F
PWM1)
)........................................................................... 1778
34-57. Control of Two Half-H Bridge Stages (F
PWM2
= N x F
PWM1
).......................................................... 1780
34-58. Half-H Bridge Waveforms for (Note: Here F
PWM2
= F
PWM1
).......................................................... 1781
34-59. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................. 1783
34-60. 3-Phase Inverter Waveforms for (Only One Inverter Shown) ..................................................... 1784
34-61. Configuring Two PWM Modules for Phase Control................................................................. 1785
34-62. Timing Waveforms Associated With Phase Control Between 2 Modules ....................................... 1786
34-63. Time-Base Status Register (TBSTS) [offset = 02h]................................................................. 1788
34-64. Time-Base Control Register (TBCTL) [offset = 00h] ................................................................ 1789
34-65. Time-Base Phase Register (TBPHS) [offset = 06h] ................................................................ 1791
34-66. Time-Base Period Register (TBPRD) [offset = 0Ah] ................................................................ 1791
34-67. Time-Base Counter Register (TBCTR) [offset = 08h] .............................................................. 1791
34-68. Counter-Compare Control Register (CMPCTL) [offset = 0Eh] .................................................... 1792
34-69. Counter-Compare A Register (CMPA) [offset = 12h]............................................................... 1793
34-70. Counter-Compare B Register (CMPB) [offset = 14h]............................................................... 1794
34-71. Action-Qualifier Output A Control Register (AQCTLA) [offset = 16h] ............................................ 1795
63
SPNU562–May 2014 List of Figures
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