Datasheet

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31-40. Transmit Control Register (TXCONTROL) (offset = 04h).......................................................... 1600
31-41. Transmit Teardown Register (TXTEARDOWN) (offset = 08h).................................................... 1601
31-42. Receive Revision ID Register (RXREVID) (offset = 10h) .......................................................... 1601
31-43. Receive Control Register (RXCONTROL) (offset = 14h) .......................................................... 1602
31-44. Receive Teardown Register (RXTEARDOWN) (offset = 18h) .................................................... 1602
31-45. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) (offset = 80h) ............................ 1603
31-46. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) (offset = 84h) .......................... 1604
31-47. Transmit Interrupt Mask Set Register (TXINTMASKSET) (offset = 88h) ........................................ 1605
31-48. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) (offset = 8Ch).................................. 1606
31-49. MAC Input Vector Register (MACINVECTOR) (offset = 90h) ..................................................... 1607
31-50. MAC End Of Interrupt Vector Register (MACEOIVECTOR) (offset = 94h)...................................... 1608
31-51. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) (offset = A0h) ............................ 1609
31-52. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) (offset = A4h)........................... 1610
31-53. Receive Interrupt Mask Set Register (RXINTMASKSET) (offset = A8h) ........................................ 1611
31-54. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) (offset = ACh).................................. 1612
31-55. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) (offset = B0h).............................. 1613
31-56. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) (offset = B4h) ............................ 1613
31-57. MAC Interrupt Mask Set Register (MACINTMASKSET) (offset = B8h) .......................................... 1614
31-58. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) (offset = BCh) ................................... 1614
31-59. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) (offset = 100h) .. 1615
31-60. Receive Unicast Enable Set Register (RXUNICASTSET) (offset = 104h) ...................................... 1617
31-61. Receive Unicast Clear Register (RXUNICASTCLEAR) (offset = 108h).......................................... 1618
31-62. Receive Maximum Length Register (RXMAXLEN) (offset = 10Ch) .............................................. 1618
31-63. Receive Buffer Offset Register (RXBUFFEROFFSET) (offset = 110h) .......................................... 1619
31-64. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) (offset = 114h).......... 1619
31-65. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) (offset = 120h-13Ch).......... 1620
31-66. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) (offset = 140h-15Ch) ................. 1620
31-67. MAC Control Register (MACCONTROL) (offset = 160h) .......................................................... 1621
31-68. MAC Status Register (MACSTATUS) (offset = 164h).............................................................. 1623
31-69. Emulation Control Register (EMCONTROL) (offset = 168h) ...................................................... 1625
31-70. FIFO Control Register (FIFOCONTROL) (offset = 16Ch) ......................................................... 1625
31-71. MAC Configuration Register (MACCONFIG) (offset = 170h)...................................................... 1626
31-72. Soft Reset Register (SOFTRESET) (offset = 174h) ................................................................ 1626
31-73. MAC Source Address Low Bytes Register (MACSRCADDRLO) (offset = 1D0h) .............................. 1627
31-74. MAC Source Address High Bytes Register (MACSRCADDRHI) (offset = 1D4h) .............................. 1627
31-75. MAC Hash Address Register 1 (MACHASH1) (offset = 1D8h) ................................................... 1628
31-76. MAC Hash Address Register 2 (MACHASH2) (offset = 1DCh) ................................................... 1628
31-77. Back Off Random Number Generator Test Register (BOFFTEST) (offset = 1E0h)............................ 1629
31-78. Transmit Pacing Algorithm Test Register (TPACETEST) (offset = 1E4h) ....................................... 1629
31-79. Receive Pause Timer Register (RXPAUSE) (offset = 1E8h)...................................................... 1630
31-80. Transmit Pause Timer Register (TXPAUSE) (offset = 1ECh) ..................................................... 1630
31-81. MAC Address Low Bytes Register (MACADDRLO) (offset = 500h).............................................. 1631
31-82. MAC Address High Bytes Register (MACADDRHI) (offset = 504h) .............................................. 1632
31-83. MAC Index Register (MACINDEX) (offset = 508h) ................................................................. 1632
31-84. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) (offset = 600h-61Ch)............... 1633
31-85. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) (offset = 620h-63Ch) ............... 1633
31-86. Transmit Channel n Completion Pointer Register (TXnCP) (offset = 640h-65Ch) ............................. 1634
31-87. Receive Channel n Completion Pointer Register (RXnCP) (offset = 660h-67Ch).............................. 1634
31-88. Statistics Register ....................................................................................................... 1635
60
List of Figures SPNU562–May 2014
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