Datasheet
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30-31. I2C Pin Direction Register (I2CPDIR) [offset = 4Ch] ............................................................... 1518
30-32. I2C Data Input Register (I2CDIN) [offset = 50h] .................................................................... 1518
30-33. I2C Data Output Register (I2CDOUT) [offset 0x54] ................................................................ 1519
30-34. I2C Data Set Register (I2CDSET) [offset = 58h].................................................................... 1519
30-35. I2C Data Clear Register (I2CDCLR) [offset = 5Ch]................................................................. 1520
30-36. I2C Pin Open Drain Register (I2CPDR) [offset = 60h] ............................................................. 1520
30-37. I2C Pull Disable Register (I2CPDIS) [offset = 64h] ................................................................. 1521
30-38. I2C Pull Select Register (I2CPSEL) [offset = 68h].................................................................. 1521
30-39. I2C Pins Slew Rate Select Register (I2CSRS) [offset = 6Ch]..................................................... 1522
30-40. Difference between Normal Operation and Backward Compatibility Mode...................................... 1523
31-1. EMAC and MDIO Block Diagram ..................................................................................... 1526
31-2. Ethernet Configuration—MII Connections ........................................................................... 1528
31-3. Ethernet Configuration—RMII Connections.......................................................................... 1530
31-4. Ethernet Frame Format................................................................................................. 1532
31-5. Basic Descriptor Format................................................................................................ 1533
31-6. Typical Descriptor Linked List ......................................................................................... 1534
31-7. Transmit Buffer Descriptor Format.................................................................................... 1537
31-8. Receive Buffer Descriptor Format..................................................................................... 1540
31-9. EMAC Control Module Block Diagram ............................................................................... 1544
31-10. MDIO Module Block Diagram.......................................................................................... 1545
31-11. EMAC Module Block Diagram ......................................................................................... 1550
31-12. EMAC Control Module Revision ID Register (REVID) (offset = 00h)............................................. 1572
31-13. EMAC Control Module Software Reset Register (SOFTRESET) (offset = 04h) ................................ 1572
31-14. EMAC Control Module Interrupt Control Register (INTCONTROL) (offset = 0Ch) ............................. 1573
31-15. EMAC Control Module Receive Threshold Interrupt Enable Register (C0RXTHRESHEN) (offset = 10h) .. 1574
31-16. EMAC Control Module Receive Interrupt Enable Register (C0RXEN) (offset = 14h).......................... 1575
31-17. EMAC Control Module Transmit Interrupt Enable Register (C0TXEN) (offset = 18h) ......................... 1576
31-18. EMAC Control Module Miscellaneous Interrupt Enable Register (C0MISCEN) (offset = 1Ch) ............... 1577
31-19. EMAC Control Module Receive Threshold Interrupt Status Register (C0RXTHRESHSTAT) (offset = 40h) 1578
31-20. EMAC Control Module Receive Interrupt Status Register (C0RXSTAT) (offset = 44h) ....................... 1579
31-21. EMAC Control Module Transmit Interrupt Status Register (C0TXSTAT) (offset = 48h) ....................... 1580
31-22. EMAC Control Module Miscellaneous Interrupt Status Register (C0MISCSTAT) (offset = 4Ch)............. 1581
31-23. EMAC Control Module Receive Interrupts Per Millisecond Register (C0RXIMAX) (offset = 70h)............ 1582
31-24. EMAC Control Module Transmit Interrupts Per Millisecond Register (C0TXIMAX) (offset = 74h) ........... 1583
31-25. MDIO Revision ID Register (REVID) (offset = 00h) ................................................................ 1584
31-26. MDIO Control Register (CONTROL) (offset = 04h)................................................................. 1585
31-27. PHY Acknowledge Status Register (ALIVE) (offset = 08h) ........................................................ 1586
31-28. PHY Link Status Register (LINK) (offset = 0Ch) .................................................................... 1586
31-29. MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) (offset = 10h).................... 1587
31-30. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) (offset = 14h) .................. 1588
31-31. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) (offset = 20h)........... 1589
31-32. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) (offset = 24h) ......... 1590
31-33. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) (offset = 28h)........ 1591
31-34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) (offset = 2Ch) . 1592
31-35. MDIO User Access Register 0 (USERACCESS0) (offset = 80h) ................................................. 1593
31-36. MDIO User PHY Select Register 0 (USERPHYSEL0) (offset = 84h) ............................................ 1594
31-37. MDIO User Access Register 1 (USERACCESS1) (offset = 88h) ................................................. 1595
31-38. MDIO User PHY Select Register 1 (USERPHYSEL1) (offset = 8Ch)............................................ 1596
31-39. Transmit Revision ID Register (TXREVID) (offset = 00h).......................................................... 1600
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SPNU562–May 2014 List of Figures
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